From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87BA4352C35 for ; Tue, 10 Mar 2026 09:45:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.118.77.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773135944; cv=none; b=TvbQix2R0AJ+PqQMdXnjQPyiin/JZNuWlcj05ZSzNQABaDV8hkx91fg/nAsOUtXXKNbtqWKct1CsclvZu6JolbAzfP2i8b6A+5RNfC/ZhP3oU0p5oxLXiFb9XCHqect2sIEdXcKvyd7KI4AfJ5hFyjHROGLZHJp16GEVR+/Y134= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773135944; c=relaxed/simple; bh=ZLvezuR8s0+OWVqfo92KUk4UlTJ6DqfgkS4fGtPZbTw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:From:In-Reply-To: Content-Type:References; b=BaIjtSM1FPNmT9KmJrX6BKYaJR8EXX6t/hFaoyf3Fy2LKFs4ozV7f5w7Y9X1eQaPbAllQfTcVSJijugx6bppuNj7f5JyF8fHABXbEGJmAePJrVuTi8lqPz/YZzYlv4YbAzEceFUv1KmQJBny8pbpJ7mAR2kE3CzA/FAAZtedzFo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=DUa33BIc; arc=none smtp.client-ip=210.118.77.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="DUa33BIc" Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (KnoxPortal) with ESMTP id 20260310094539euoutp022280938404872dda42471ef0a5d31e7f~bcb4ubTCG0927609276euoutp02G for ; Tue, 10 Mar 2026 09:45:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.w1.samsung.com 20260310094539euoutp022280938404872dda42471ef0a5d31e7f~bcb4ubTCG0927609276euoutp02G DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1773135939; bh=g4Z4ok96NWqzBgjOcLsFlXJfC/4zjtxkfiYjt2twx7A=; h=Date:Subject:To:Cc:From:In-Reply-To:References:From; b=DUa33BIcjnjYaDcrUwR4b3y4tN6gJrXkmaBcwcJ4p2c4tZGQM9R38aSaC2a0O/Bbo 0xa64kwxr8dc0Yov8gz0+bhz5Z3p5QxpyUFH3txM4dysJYcWw+sParNspVxK2j8cYf dHSDbRa7PdBI1Opg2OUQSyeLHuC0MQYAqRPXhB3s= Received: from eusmtip1.samsung.com (unknown [203.254.199.221]) by eucas1p1.samsung.com (KnoxPortal) with ESMTPA id 20260310094539eucas1p15d2320cc87bfb317f5be51b359fb08c6~bcb4brfjb0410104101eucas1p1p; Tue, 10 Mar 2026 09:45:39 +0000 (GMT) Received: from [106.210.134.192] (unknown [106.210.134.192]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20260310094538eusmtip17998daf8f2a16ee4d9b5c8cb775d1e36~bcb3virLM2940529405eusmtip1i; Tue, 10 Mar 2026 09:45:38 +0000 (GMT) Message-ID: Date: Tue, 10 Mar 2026 10:45:38 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Betterbird (Windows) Subject: Re: [PATCH 2/3] dma-mapping: Clarify valid conditions for CPU cache line overlap To: Jason Gunthorpe , Leon Romanovsky Cc: Robin Murphy , "Michael S. Tsirkin" , Petr Tesarik , Jonathan Corbet , Shuah Khan , Jason Wang , Xuan Zhuo , =?UTF-8?Q?Eugenio_P=C3=A9rez?= , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, virtualization@lists.linux.dev, linux-rdma@vger.kernel.org Content-Language: en-US From: Marek Szyprowski In-Reply-To: <20260309151356.GN1687929@ziepe.ca> Content-Transfer-Encoding: 7bit X-CMS-MailID: 20260310094539eucas1p15d2320cc87bfb317f5be51b359fb08c6 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20260309090352eucas1p283a75c78cac495b5ad87df74c79aab07 X-EPHeader: CA X-CMS-RootMailID: 20260309090352eucas1p283a75c78cac495b5ad87df74c79aab07 References: <20260307-dma-debug-overlap-v1-0-c034c38872af@nvidia.com> <20260307-dma-debug-overlap-v1-2-c034c38872af@nvidia.com> <20260308181920.GH1687929@ziepe.ca> <20260308184902.GR12611@unreal> <20260308230916.GI1687929@ziepe.ca> <20260309090342.GS12611@unreal> <20260309150502.GX12611@unreal> <20260309151356.GN1687929@ziepe.ca> On 09.03.2026 16:13, Jason Gunthorpe wrote: > On Mon, Mar 09, 2026 at 05:05:02PM +0200, Leon Romanovsky wrote: >> Regarding failure on unsupported systems, I have tried more than once to >> make the RDMA fail when the device is known to take the SWIOTLB path >> in RDMA and cannot operate correctly, but each attempt was met with a >> cold reception: >> https://lore.kernel.org/all/d18c454636bf3cfdba9b66b7cc794d713eadc4a5.1719909395.git.leon@kernel.org/ > I think alot of that is the APIs used there. It is hard to determine > if SWIOTLB is possible or coherent is possible, I've also hit these > things in VFIO and gave up. > > However, DMA_ATTR_REQUIRE_COHERENCE can be done properly and not leak > alot of dangerous APIs to drivers (beyond itself). > > It is also more important now with CC systems, I think. Jason is right. Indeed the rdma/uverbs case needs some extension to ensure that the coherent mapping is used, what is not possible now. This however doesn't mean that the DMA_ATTR_CPU_CACHE_OVERLAP is not needed for that use case too. I'm open to accept both. The only question I have is which name should we use? We already have DMA_ATTR_CPU_CACHE_CLEAN, while DMA_ATTR_CPU_CACHE_OVERLAP and DMA_ATTR_DEBUGGING_IGNORE_CACHELINES were proposed here. The last seems to be most descriptive. Best regards -- Marek Szyprowski, PhD Samsung R&D Institute Poland