From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAFC9C43381 for ; Thu, 14 Feb 2019 15:51:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 95C82222DA for ; Thu, 14 Feb 2019 15:51:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2395120AbfBNPva (ORCPT ); Thu, 14 Feb 2019 10:51:30 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:46164 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388168AbfBNPv3 (ORCPT ); Thu, 14 Feb 2019 10:51:29 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EE233EBD; Thu, 14 Feb 2019 07:51:28 -0800 (PST) Received: from [10.1.196.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B5AF93F575; Thu, 14 Feb 2019 07:51:25 -0800 (PST) Subject: Re: [PATCH v2 01/14] dt-bindings: remoteproc: Add TI PRUSS bindings To: Roger Quadros , Suman Anna , "Davis, Andrew" , Lokesh Vutla Cc: Linus Walleij , ext Tony Lindgren , Ohad Ben-Cohen , Bjorn Andersson , David Lechner , "Nori, Sekhar" , Tero Kristo , nsaulnier@ti.com, jreeder@ti.com, Murali Karicheri , woods.technical@gmail.com, Linux-OMAP , linux-remoteproc@vger.kernel.org, "linux-kernel@vger.kernel.org" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" References: <1549290167-876-1-git-send-email-rogerq@ti.com> <1549290167-876-2-git-send-email-rogerq@ti.com> <9c58bc48-90bf-8ac5-7fbd-0f6443e3fc5e@ti.com> <5C65490E.6000800@ti.com> <86ef8asfap.wl-marc.zyngier@arm.com> <5C658CE4.5030307@ti.com> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: <5C658CE4.5030307@ti.com> Content-Type: text/plain; charset=windows-1252 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/02/2019 15:44, Roger Quadros wrote: > On 14/02/19 14:52, Marc Zyngier wrote: >> On Thu, 14 Feb 2019 10:55:10 +0000, >> Roger Quadros wrote: >>> >>> >>> On 14/02/19 10:37, Linus Walleij wrote: >>>> On Thu, Feb 14, 2019 at 4:13 AM Suman Anna wrote: >>>>> [Me] >>>> >>>>>> To be able to use hierarchical interrupt domain in the kernel, the top >>>>>> interrupt controller must use the hierarchical (v2) irqdomain, so >>>>>> if this is anything else than the ARM GIC it will be an interesting >>>>>> undertaking to handle this. >>>>> >>>>> These are interrupt lines coming towards the host processor running >>>>> Linux and are directly connected to the ARM GIC. This INTC module is >>>>> actually an PRUSS internal interrupt controller that can take in 64 (on >>>>> most SoCs) external events/interrupt sources and multiplexing them >>>>> through two layers of many-to-one events-to-intr channels & >>>>> intr-channels-to-host interrupts. Couple of the host interrupts go to >>>>> the PRU cores themselves while the remaining ones come out of the IP to >>>>> connect to other GICs in the SoC. >>>> >>>> If the muxing is static (like set up once at probe) so that while >>>> the system is running, there is one and one only event mapped to >>>> the GIC from the component below it, then it is hierarchical. >>> >>> This is how it looks. >>> >>> [GIC]<---8---[INTC]<---64---[events from peripherals] >>> >>> The 8 interrupt lines from INTC to the GIC are 1:1 mapped and fixed >>> per SoC. The muxing between 64 inputs to INTC and its 8 outputs are >>> programmable and might not necessarily be static per boot/probe as >>> it depends on what firmware is loaded on the PRU. >> >> But the point is that at any given time, there are at most 8 out of 64 >> inputs that are used, right? You *never* end-up with two (or more) of >> these "events" being multiplexed on a single output line. >> > > Since the INTC's internal logic allows assigning more than one event each outputs, > at most all 64 events can be assigned to one output or distributed among the 8 outputs. OK. Do you get individual masking and status bits for each input? Thanks, M. -- Jazz is not dead. It just smells funny...