From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1046B361DAB for ; Wed, 4 Mar 2026 20:29:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772656143; cv=none; b=nG/78gqSDE+yds/9sC9CrgqAHpsrSZLlnc4DAKjvhsADUv8gHsSHp6wXTF72cOnNX7LBOQOx56M4dNAZyUdTLBlWSR/vXFOfD+1bLmg0yMiOz8paN4tCQ6V9cjOyv3zIa0F0FvFxJB5O2S09GdBG9xpHRqp8AV2M1mHMwnIdfLI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772656143; c=relaxed/simple; bh=GG34XFUL2Z/QzJh6ZOi3J7m7pp7Q4TByKM0to7E+/hU=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition; b=JgJ/95z6W0ME4p9+uPAlIyDhHISqWdlMR4t6AXIpMvuwvKLSlioWhwR5pzjO+3VYPLpDTDs0EkNty7FHh+nUT9mNOShm2tyiDag7KgcqXIkQbKGeEbU5s7bpPSpTZNC+xZikrXL1HNneYnlGigqBvDviSHJ3vEow3d21hs+9BLU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=b4CUcU/F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="b4CUcU/F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6C93EC4CEF7; Wed, 4 Mar 2026 20:29:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772656142; bh=GG34XFUL2Z/QzJh6ZOi3J7m7pp7Q4TByKM0to7E+/hU=; h=Date:From:To:Cc:Subject:From; b=b4CUcU/FfUG+vkM7vccMOxWWhODXZjGeD6OXXmvBHJgXL0lHQBqaDXvRqYNsgbG1r KiixB6tCbU2cqPdtgVMl4IwNpBwX5Mb64TptuTr6WGzeREFvVLop9eP5WFfncE7wwT sPPUHn0TIdyZBuK16LYQktT0vIAqpX7TyV4Ot19VBd0jADipkiho9HWg5phJ6SfuUK DS7IEA4fM4zbwKqSunYjcvk32nzBxJVXI+C8rcoo4eMimK4gjNzkUQaEb8gOfSG4Cq Ymbb0Z9HsaD0LCUABot/oM9U7yhr4GEvhmUztdt5jaAlAAm5eeeXpN0Ig4LpW+zXVi HFhxWWV5cvRZw== Date: Wed, 4 Mar 2026 17:28:59 -0300 From: Arnaldo Carvalho de Melo To: linux-kernel@vger.kernel.org Cc: Borislav Petkov , Dapeng Mi , Peter Zijlstra , Sean Christopherson , Adrian Hunter , Ian Rogers , James Clark , Jiri Olsa , Namhyung Kim Subject: [PATCH 1/1 fyi] tools arch x86: Sync msr-index.h to pick MSR_{OMR_[0-3],CORE_PERF_GLOBAL_STATUS_SET} Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline tldr; Just FYI, I'm carrying this on the perf tools tree. Full explanation: There used to be no copies, with tools/ code using kernel headers directly. From time to time tools/perf/ broke due to legitimate kernel hacking. At some point Linus complained about such direct usage. Then we adopted the current model. See further details at: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/include/uapi/README To pick up the changes in: 4e955c08d6dc76fb ("perf/x86/intel: Support the 4 new OMR MSRs introduced in DMR and NVL") 736a2dcfdae72483 ("x86/CPU/AMD: Simplify the spectral chicken fix") 56bb2736975068cc ("KVM: x86/pmu: Load/put mediated PMU context when entering/exiting guest") Addressing this tools/perf build warning: Warning: Kernel ABI header differences: diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h That makes the beautification scripts to pick some new entries: $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before.txt $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after.txt $ diff -u before.txt after.txt --- before.txt 2026-03-04 17:21:39.165956041 -0300 +++ after.txt 2026-03-04 17:21:52.479191640 -0300 @@ -130,6 +130,11 @@ [0x0000038e] = "CORE_PERF_GLOBAL_STATUS", [0x0000038f] = "CORE_PERF_GLOBAL_CTRL", [0x00000390] = "CORE_PERF_GLOBAL_OVF_CTRL", + [0x00000391] = "CORE_PERF_GLOBAL_STATUS_SET", + [0x000003e0] = "OMR_0", + [0x000003e1] = "OMR_1", + [0x000003e2] = "OMR_2", + [0x000003e3] = "OMR_3", [0x000003f1] = "IA32_PEBS_ENABLE", [0x000003f2] = "PEBS_DATA_CFG", [0x000003f4] = "IA32_PEBS_BASE", $ Now one can use those strings in 'perf trace' to do filtering, e.g.: # perf trace -e msr:*_msr/max-stack=32/ --filter="msr==CORE_PERF_GLOBAL_STATUS_SET" Cc: Borislav Petkov (AMD) Cc: Dapeng Mi Cc: Peter Zijlstra Cc: Sean Christopherson Signed-off-by: Arnaldo Carvalho de Melo --- tools/arch/x86/include/asm/msr-index.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 43adc38d31d57539..da5275d8eda63e19 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -263,6 +263,11 @@ #define MSR_SNOOP_RSP_0 0x00001328 #define MSR_SNOOP_RSP_1 0x00001329 +#define MSR_OMR_0 0x000003e0 +#define MSR_OMR_1 0x000003e1 +#define MSR_OMR_2 0x000003e2 +#define MSR_OMR_3 0x000003e3 + #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 @@ -1219,6 +1224,7 @@ #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 +#define MSR_CORE_PERF_GLOBAL_STATUS_SET 0x00000391 #define MSR_PERF_METRICS 0x00000329 -- 2.53.0