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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be2c9c67dbsm3371059eec.19.2026.03.05.00.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 00:40:43 -0800 (PST) Date: Thu, 5 Mar 2026 00:40:42 -0800 From: Qiang Yu To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/5] arch: arm64: dts: qcom: Add support for PCIe3a Message-ID: References: <20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com> <20260304-glymur_gen5x8_phy-v1-5-849e9a72e125@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA2OCBTYWx0ZWRfX6Buj1R6Tpb16 IraomTEtCD+Bdg1cxEQfkqH+yUW6oR2DtaW3JxU3v6N46qcCliE7Ul7LrjEZoONfglY+3fljPIC +3qMnHCRbooWtOG38cC6jKa+CoR4Rl/B/lvWOmJcIjKVhHeve9jz1hDbcVJW4wQfTapEhN4FNd5 uuzMo6iOjDE+giHQX8biPu+XTfvHCHysVqmpeDDLtOwhhtM8p2eKqeSNWhOCjEP7SZZQjSme5QZ tsyRXgzZLZUvDpTxCnWiO1BeqVXE8gQtrtCZFe9mZfTV/6O+kZmarTtOEaGORSOvbatkAlVbrGz iLV9HW+8bv8YO4WM7z1gXhSOZrbuAPFbTE23v0vfIGdEm5/puTsIHFPKsnSpWCQppFQN9nJTUsE l7Uo0giiIEOfVXR8iwRz2v8skvc6zf7grIEm1xupX+U8IHpbAHXooCQKi7ZJ9WmCNx0kwAqMrny r6xao+gNsCtv6PAI5uQ== X-Proofpoint-ORIG-GUID: lB8KzOIlCxhFm4BjcHYBti_ru91MryOx X-Authority-Analysis: v=2.4 cv=Ddsaa/tW c=1 sm=1 tr=0 ts=69a9418d cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=6aSL9Ysz0BH7CvPNE-sA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: lB8KzOIlCxhFm4BjcHYBti_ru91MryOx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_02,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050068 On Thu, Mar 05, 2026 at 02:02:18AM +0200, Dmitry Baryshkov wrote: > On Wed, Mar 04, 2026 at 12:21:59AM -0800, Qiang Yu wrote: > > Describe PCIe3a controller and PHY. Also add required system resources > > like regulators, clocks, interrupts and registers configuration for PCIe3a. > > > > Signed-off-by: Qiang Yu > > --- > > arch/arm64/boot/dts/qcom/glymur.dtsi | 314 ++++++++++++++++++++++++++++++++++- > > 1 file changed, 313 insertions(+), 1 deletion(-) > > > > + pcie3a_phy: phy@f00000 { > > + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; > > + reg = <0 0x00f00000 0 0x10000>; > > + > > + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, > > + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, > > + <&tcsr TCSR_PCIE_3_CLKREF_EN>, > > + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, > > + <&gcc GCC_PCIE_3A_PIPE_CLK>, > > + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>; > > + clock-names = "aux", > > + "cfg_ahb", > > + "ref", > > + "rchng", > > Please align on " Okay, will align on " in next version. > > > + "pipe", > > + "phy_b_aux"; > > + > > + resets = <&gcc GCC_PCIE_3A_PHY_BCR>, > > + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, > > + <&gcc GCC_PCIE_3B_PHY_BCR>, > > + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; > > + reset-names = "phy", > > + "phy_nocsr", > > + "phy_b", > > + "phy_b_nocsr"; > > Should we be supplying _b components by default? What about the > platforms which might use separate 3a and 3b? We can override compatible, resets, and clks in board.dts. - Qiang Yu > > > + > > + assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>; > > + assigned-clock-rates = <100000000>; > > + > > + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, > > + <&gcc GCC_PCIE_3B_PHY_GDSC>; > > + > > + #clock-cells = <0>; > > + clock-output-names = "pcie3a_pipe_clk"; > > + > > + #phy-cells = <0>; > > + > > + status = "disabled"; > > + }; > > + > > pcie4: pci@1bf0000 { > > device_type = "pci"; > > compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; > > > > -- > > 2.34.1 > > > > -- > With best wishes > Dmitry