From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 824294400; Tue, 29 Oct 2024 02:50:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730170257; cv=none; b=qOp7o1XTnUeX4j09bZ+ocCTLs9YhMCL3bmqxVX+ISekuUS+JojlrD9PDpkzQ3ELilayVMEsgaCUY377KJnxUuMAeJwgMQfa7+VqcGz7pBLUjPyuL3qJ5bmh6iAZSr+hfHYc6Xwqu8ZxMDOAwK10Tx0qnoY0dOHpiOhmATRQ6n1U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730170257; c=relaxed/simple; bh=rbs6zdmlmEO16BukbbW/kX6BRAgAHqPcAzpnhOyj4wA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=pozc/dF0p6jWSRMTvj78GQhtV3BlssBl79YnVQlClRcb0dBLjD84sUdbWflqfv2HZhjYd+k28Fv39+PFQH5nMCIzaAk9dSZXwCkttaEGCrNqcmsSXvvU8IKPfE+AuXcHrvhr4wN5BSP/ZBef3aqGJ9w3LrTLpBGy83h2AzNiJYo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=dvKgnwL+; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="dvKgnwL+" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=4x7+NMYuwtDNvuiXxIkan9s38gNFO7jrlobgIQdg9wI=; b=dvKgnwL+xlxDZYgcteGPA7b1b7 mLcb/Toa8r1YLBarjgVedww/AUh/e93nYKxJn0MCiIuXh1j8B+aBur60A4HEBBxqIfiLMvlt4rF0O 7jPcAv+gcq+yNAuTKebC5HnZ9CB2ptTJoX+sj2mDMLGrqaP5KDvKrRk1CSAhwJWRWCDY=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1t5cJd-00BWHU-42; Tue, 29 Oct 2024 03:50:41 +0100 Date: Tue, 29 Oct 2024 03:50:41 +0100 From: Andrew Lunn To: Inochi Amaoto Cc: Chen Wang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Richard Cochran , Jisheng Zhang , Thomas Bonnefille , Liu Gui , Yixun Lan , Longbin Li , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH] riscv: dts: sophgo: Add ethernet configuration for cv18xx Message-ID: References: <20241028011312.274938-1-inochiama@gmail.com> <87e215a7-0b27-4336-9f9c-e63ade0772ef@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Oct 29, 2024 at 06:43:03AM +0800, Inochi Amaoto wrote: > On Mon, Oct 28, 2024 at 02:09:06PM +0100, Andrew Lunn wrote: > > > +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi > > > @@ -210,6 +210,55 @@ i2c4: i2c@4040000 { > > > status = "disabled"; > > > }; > > > > > > + gmac0: ethernet@4070000 { > > > + compatible = "snps,dwmac-3.70a"; > > > + reg = <0x04070000 0x10000>; > > > + clocks = <&clk CLK_AXI4_ETH0>, <&clk CLK_ETH0_500M>; > > > + clock-names = "stmmaceth", "ptp_ref"; > > > + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "macirq"; > > > + phy-handle = <&phy0>; > > > + phy-mode = "rmii"; > > > + rx-fifo-depth = <8192>; > > > + tx-fifo-depth = <8192>; > > > + snps,multicast-filter-bins = <0>; > > > + snps,perfect-filter-entries = <1>; > > > + snps,aal; > > > + snps,txpbl = <8>; > > > + snps,rxpbl = <8>; > > > + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; > > > + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; > > > + snps,axi-config = <&gmac0_stmmac_axi_setup>; > > > + status = "disabled"; > > > + > > > + mdio { > > > + compatible = "snps,dwmac-mdio"; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + phy0: phy@0 { > > > + compatible = "ethernet-phy-ieee802.3-c22"; > > > + reg = <0>; > > > + }; > > > + }; > > > > It is not clear to me what cv18xx.dtsi represents, > > This is a include file to define common ip for the whole > cv18xx series SoCs (cv1800b, cv1812h, sg2000, sg2000). > > > and where the PHY node should be, here, or in a .dts file. > > Is this a SOM, and the PHY is on the SOM? > > The phy is on the SoC, it is embedded, and no external phy > is supported. So I think the phy node should stay here, not > in the dts file. So this is correct when the PHY is internal. However, this is normally expressed by setting phy-mode to "internal". The stmmac driver might however not allow that? If not, please put a comment indicating the PHY is part of the SoC. Andrew