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Wed, 18 Dec 2024 14:54:57 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id kG/9OEHiYmfBLAAAD6G6ig (envelope-from ); Wed, 18 Dec 2024 14:54:57 +0000 Message-ID: Date: Wed, 18 Dec 2024 16:54:57 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/10] PCI: brcmstb: Enable external MSI-X if available To: James Quinlan , Stanimir Varbanov , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rpi-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Broadcom internal kernel review list Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Jim Quinlan , Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , kw@linux.com, Philipp Zabel , Andrea della Porta , Phil Elwell , Jonathan Bell References: <20241025124515.14066-1-svarbanov@suse.de> <20241025124515.14066-7-svarbanov@suse.de> Content-Language: en-US From: Stanimir Varbanov In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Score: -2.80 X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-0.999]; MIME_GOOD(-0.10)[text/plain]; RCVD_TLS_ALL(0.00)[]; TAGGED_RCPT(0.00)[dt]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[22]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[linutronix.de,kernel.org,broadcom.com,gmail.com,google.com,linux.com,pengutronix.de,suse.com,raspberrypi.com]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_BLOCKED(0.00)[rspamd.com]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.de:mid,suse.de:email] X-Spam-Flag: NO X-Spam-Level: Hi Jim, Thanks for comments! On 12/11/24 10:01 PM, James Quinlan wrote: > On 10/25/24 08:45, Stanimir Varbanov wrote: >> On RPi5 there is an external MIP MSI-X interrupt controller >> which can handle up to 64 interrupts. >> >> Signed-off-by: Stanimir Varbanov >> --- >> v3 -> v4: >>   - no changes. >> >>   drivers/pci/controller/pcie-brcmstb.c | 63 +++++++++++++++++++++++++-- >>   1 file changed, 59 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/ >> controller/pcie-brcmstb.c >> index c01462b07eea..af01a7915c94 100644 >> --- a/drivers/pci/controller/pcie-brcmstb.c >> +++ b/drivers/pci/controller/pcie-brcmstb.c >> @@ -1318,6 +1318,52 @@ static int brcm_pcie_start_link(struct >> brcm_pcie *pcie) >>       return 0; >>   } >>   +static int brcm_pcie_enable_external_msix(struct brcm_pcie *pcie, >> +                      struct device_node *msi_np) >> +{ >> +    struct inbound_win inbound_wins[PCIE_BRCM_MAX_INBOUND_WINS]; >> +    u64 msi_pci_addr, msi_phys_addr; >> +    struct resource r; >> +    int mip_bar, ret; >> +    u32 val, reg; >> + >> +    ret = of_property_read_reg(msi_np, 1, &msi_pci_addr, NULL); >> +    if (ret) >> +        return ret; >> + >> +    ret = of_address_to_resource(msi_np, 0, &r); >> +    if (ret) >> +        return ret; >> + >> +    msi_phys_addr = r.start; >> + >> +    /* Find free inbound window for MIP access */ >> +    mip_bar = brcm_pcie_get_inbound_wins(pcie, inbound_wins); >> +    if (mip_bar < 0) >> +        return mip_bar; >> + >> +    mip_bar += 1; >> +    reg = brcm_bar_reg_offset(mip_bar); >> + >> +    val = lower_32_bits(msi_pci_addr); >> +    val |= brcm_pcie_encode_ibar_size(SZ_4K); >> +    writel(val, pcie->base + reg); >> + >> +    val = upper_32_bits(msi_pci_addr); >> +    writel(val, pcie->base + reg + 4); >> + >> +    reg = brcm_ubus_reg_offset(mip_bar); >> + >> +    val = lower_32_bits(msi_phys_addr); >> +    val |= PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_EN_MASK; >> +    writel(val, pcie->base + reg); >> + >> +    val = upper_32_bits(msi_phys_addr); >> +    writel(val, pcie->base + reg + 4); > > Hi Stan, > > It looks like all this is doing is setting up an identity-mapped inbound > window, is that correct?  If so, couldn't you get the same effect by > adding an identity-mapped dma-range in the PCIe DT node? Yes, that approach could work, I verified it. Do you want me to drop this patch from the series and make the relevant changes in PCIe dma-ranges properties? ~Stan