Re: lapic-related boot crash in 4.15-rc1

[Dou Liyang <douly.fnst@cn.fujitsu.com>]

Hi Thomas,

At 01/16/2018 12:21 AM, Thomas Gleixner wrote:
> On Mon, 15 Jan 2018, Meelis Roos wrote:
> 
>> On Wed, 10 Jan 2018, Thomas Gleixner wrote:
>>
>>> On Wed, 10 Jan 2018, Meelis Roos wrote:
>>>
>>>>>> On 3 of my test computers, boot hangs with 4.15 git kernels. So far I
>>>>>> have traced it down to 4.14.0 being good and 4.15-rc1 being bad (bisect
>>>>>> is slow because the computers are somwehat remote). Also because of
>>>>>> trying to find when it started, I have not tries newer than rc5
>>>>>> kernels.
>>>>>
>>>>> Please do so. We have fixes post rc5 in that area.
>>>>
>>>> P4 was the quickest to rebuild the kernel and it is still hanging like
>>>> before with todays 4.15-rc7-00102-gcf1fb158230e.
>>
>> So far I have bisected it to 4f45ed9f848f good, ae41a2a40ed4 bad. Will
>> continue tomorrow.
>>
>> 1be2172e96e3 bad
>> 2cd83ba5bede bad
>> 449fcf3ab0ba bad
>> 43ff2f4db9d0 good
>> 313144c1bcd6 good
>> b18d62891aaf bad
>> b24591e2fcf8 good
>> 0696d059f23c bad
>> 023a611748fd bad
>> ae41a2a40ed4 bad
>> 4f45ed9f848f good
> 
> I've reverted the commit which Dou pointed out in rc8. Can you please confirm that
> this fixes the issue for you?
> 

Due to my email server error, it seems Meelis didn't receive my email.
Can you FWD this patch to him?

Thanks,
     dou.
--------------------------->8-----------------------------------
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This reverts commit b371ae0d4a194b178817b0edfb6a7395c7aec37a.

Causes my P3 UP machine to hang at boot with "lapic".

Cc: Dou Liyang <douly.fnst@cn.fujitsu.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: yinghai@kernel.org
Cc: bhe@redhat.com
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
  arch/x86/include/asm/apic.h |  1 +
  arch/x86/kernel/apic/apic.c | 49 
+++++++++++++++++++++++++++++++++++++++++++++
  arch/x86/kernel/irqinit.c   |  3 +++
  3 files changed, 53 insertions(+)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index a9e57f08bfa6..98722773391d 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -136,6 +136,7 @@ extern void disconnect_bsp_APIC(int virt_wire_setup);
  extern void disable_local_APIC(void);
  extern void lapic_shutdown(void);
  extern void sync_Arb_IDs(void);
+extern void init_bsp_APIC(void);
  extern void apic_intr_mode_init(void);
  extern void setup_local_APIC(void);
  extern void init_apic_mappings(void);
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 6e272f3ea984..cec9aaea7f9d 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1286,6 +1286,55 @@ static int __init apic_intr_mode_select(void)
      return APIC_SYMMETRIC_IO;
  }

+/*
+ * An initial setup of the virtual wire mode.
+ */
+void __init init_bsp_APIC(void)
+{
+    unsigned int value;
+
+    /*
+     * Don't do the setup now if we have a SMP BIOS as the
+     * through-I/O-APIC virtual wire mode might be active.
+     */
+    if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
+        return;
+
+    /*
+     * Do not trust the local APIC being empty at bootup.
+     */
+    clear_local_APIC();
+
+    /*
+     * Enable APIC.
+     */
+    value = apic_read(APIC_SPIV);
+    value &= ~APIC_VECTOR_MASK;
+    value |= APIC_SPIV_APIC_ENABLED;
+
+#ifdef CONFIG_X86_32
+    /* This bit is reserved on P4/Xeon and should be cleared */
+    if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
+        (boot_cpu_data.x86 == 15))
+        value &= ~APIC_SPIV_FOCUS_DISABLED;
+    else
+#endif
+        value |= APIC_SPIV_FOCUS_DISABLED;
+    value |= SPURIOUS_APIC_VECTOR;
+    apic_write(APIC_SPIV, value);
+
+    /*
+     * Set up the virtual wire mode.
+     */
+    apic_write(APIC_LVT0, APIC_DM_EXTINT);
+    value = APIC_DM_NMI;
+    if (!lapic_is_integrated())        /* 82489DX */
+        value |= APIC_LVT_LEVEL_TRIGGER;
+    if (apic_extnmi == APIC_EXTNMI_NONE)
+        value |= APIC_LVT_MASKED;
+    apic_write(APIC_LVT1, value);
+}
+
  /* Init the interrupt delivery mode for the BSP */
  void __init apic_intr_mode_init(void)
  {
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 8da3e909e967..a539410c4ea9 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -61,6 +61,9 @@ void __init init_ISA_irqs(void)
      struct irq_chip *chip = legacy_pic->chip;
      int i;

+#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
+    init_bsp_APIC();
+#endif
      legacy_pic->init(0);

      for (i = 0; i < nr_legacy_irqs(); i++)
---
> Thanks,
> 
> 	tglx
> 
> 
>