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Tue, 11 Nov 2025 08:59:26 -0800 (PST) Received: from [192.168.10.81] ([176.206.111.214]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-42ac679607esm28646672f8f.43.2025.11.11.08.59.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Nov 2025 08:59:23 -0800 (PST) Message-ID: Date: Tue, 11 Nov 2025 17:59:21 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v1 17/20] KVM: x86: Prepare APX state setting in XCR0 To: "Chang S. Bae" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: seanjc@google.com, chao.gao@intel.com, zhao1.liu@intel.com References: <20251110180131.28264-1-chang.seok.bae@intel.com> <20251110180131.28264-18-chang.seok.bae@intel.com> From: Paolo Bonzini Content-Language: en-US Autocrypt: addr=pbonzini@redhat.com; keydata= xsEhBFRCcBIBDqDGsz4K0zZun3jh+U6Z9wNGLKQ0kSFyjN38gMqU1SfP+TUNQepFHb/Gc0E2 CxXPkIBTvYY+ZPkoTh5xF9oS1jqI8iRLzouzF8yXs3QjQIZ2SfuCxSVwlV65jotcjD2FTN04 hVopm9llFijNZpVIOGUTqzM4U55sdsCcZUluWM6x4HSOdw5F5Utxfp1wOjD/v92Lrax0hjiX DResHSt48q+8FrZzY+AUbkUS+Jm34qjswdrgsC5uxeVcLkBgWLmov2kMaMROT0YmFY6A3m1S P/kXmHDXxhe23gKb3dgwxUTpENDBGcfEzrzilWueOeUWiOcWuFOed/C3SyijBx3Av/lbCsHU Vx6pMycNTdzU1BuAroB+Y3mNEuW56Yd44jlInzG2UOwt9XjjdKkJZ1g0P9dwptwLEgTEd3Fo UdhAQyRXGYO8oROiuh+RZ1lXp6AQ4ZjoyH8WLfTLf5g1EKCTc4C1sy1vQSdzIRu3rBIjAvnC tGZADei1IExLqB3uzXKzZ1BZ+Z8hnt2og9hb7H0y8diYfEk2w3R7wEr+Ehk5NQsT2MPI2QBd wEv1/Aj1DgUHZAHzG1QN9S8wNWQ6K9DqHZTBnI1hUlkp22zCSHK/6FwUCuYp1zcAEQEAAc0j UGFvbG8gQm9uemluaSA8cGJvbnppbmlAcmVkaGF0LmNvbT7CwU0EEwECACMFAlRCcBICGwMH CwkIBwMCAQYVCAIJCgsEFgIDAQIeAQIXgAAKCRB+FRAMzTZpsbceDp9IIN6BIA0Ol7MoB15E 11kRz/ewzryFY54tQlMnd4xxfH8MTQ/mm9I482YoSwPMdcWFAKnUX6Yo30tbLiNB8hzaHeRj jx12K+ptqYbg+cevgOtbLAlL9kNgLLcsGqC2829jBCUTVeMSZDrzS97ole/YEez2qFpPnTV0 VrRWClWVfYh+JfzpXmgyhbkuwUxNFk421s4Ajp3d8nPPFUGgBG5HOxzkAm7xb1cjAuJ+oi/K CHfkuN+fLZl/u3E/fw7vvOESApLU5o0icVXeakfSz0LsygEnekDbxPnE5af/9FEkXJD5EoYG SEahaEtgNrR4qsyxyAGYgZlS70vkSSYJ+iT2rrwEiDlo31MzRo6Ba2FfHBSJ7lcYdPT7bbk9 AO3hlNMhNdUhoQv7M5HsnqZ6unvSHOKmReNaS9egAGdRN0/GPDWr9wroyJ65ZNQsHl9nXBqE AukZNr5oJO5vxrYiAuuTSd6UI/xFkjtkzltG3mw5ao2bBpk/V/YuePrJsnPFHG7NhizrxttB nTuOSCMo45pfHQ+XYd5K1+Cv/NzZFNWscm5htJ0HznY+oOsZvHTyGz3v91pn51dkRYN0otqr bQ4tlFFuVjArBZcapSIe6NV8C4cEiSTOwE0EVEJx7gEIAMeHcVzuv2bp9HlWDp6+RkZe+vtl KwAHplb/WH59j2wyG8V6i33+6MlSSJMOFnYUCCL77bucx9uImI5nX24PIlqT+zasVEEVGSRF m8dgkcJDB7Tps0IkNrUi4yof3B3shR+vMY3i3Ip0e41zKx0CvlAhMOo6otaHmcxr35sWq1Jk tLkbn3wG+fPQCVudJJECvVQ//UAthSSEklA50QtD2sBkmQ14ZryEyTHQ+E42K3j2IUmOLriF dNr9NvE1QGmGyIcbw2NIVEBOK/GWxkS5+dmxM2iD4Jdaf2nSn3jlHjEXoPwpMs0KZsgdU0pP JQzMUMwmB1wM8JxovFlPYrhNT9MAEQEAAcLBMwQYAQIACQUCVEJx7gIbDAAKCRB+FRAMzTZp sadRDqCctLmYICZu4GSnie4lKXl+HqlLanpVMOoFNnWs9oRP47MbE2wv8OaYh5pNR9VVgyhD OG0AU7oidG36OeUlrFDTfnPYYSF/mPCxHttosyt8O5kabxnIPv2URuAxDByz+iVbL+RjKaGM GDph56ZTswlx75nZVtIukqzLAQ5fa8OALSGum0cFi4ptZUOhDNz1onz61klD6z3MODi0sBZN Aj6guB2L/+2ZwElZEeRBERRd/uommlYuToAXfNRdUwrwl9gRMiA0WSyTb190zneRRDfpSK5d usXnM/O+kr3Dm+Ui+UioPf6wgbn3T0o6I5BhVhs4h4hWmIW7iNhPjX1iybXfmb1gAFfjtHfL xRUr64svXpyfJMScIQtBAm0ihWPltXkyITA92ngCmPdHa6M1hMh4RDX+Jf1fiWubzp1voAg0 JBrdmNZSQDz0iKmSrx8xkoXYfA3bgtFN8WJH2xgFL28XnqY4M6dLhJwV3z08tPSRqYFm4NMP dRsn0/7oymhneL8RthIvjDDQ5ktUjMe8LtHr70OZE/TT88qvEdhiIVUogHdo4qBrk41+gGQh b906Dudw5YhTJFU3nC6bbF2nrLlB4C/XSiH76ZvqzV0Z/cAMBo5NF/w= In-Reply-To: <20251110180131.28264-18-chang.seok.bae@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/10/25 19:01, Chang S. Bae wrote: > Prepare the APX state enabling in XCR0 by implementing the previous > placeholders and ensuring its readiness. > > APX introduces EGPRs, tracked as XSTATE component 19. Like other > XSAVE-managed states, EGPR availability is controlled through XCR0, and > the registers are accessible only in 64-bit mode. > > At this point, only VMX supports EGPRs. SVM will require corresponding > extensions to handle EGPR indices. > > The addition to the supported XCR0 mask should accompany guest CPUID > exposure, which will be done separately. You should also adjust set_xcr to reject setting BNDREGS and APX together (QEMU should also reject MPX and APX together in CPUID, but KVM doesn't care enough about invalid CPUID configuration). Paolo > > Signed-off-by: Chang S. Bae > --- > RFC note > Not all callers may need to validate the XCR0 bit -- maybe a capability > bit. However, every exit associated with EGPRs should already have that > control bit set in the first place. Checking it explicitly does not > charge additional cost, so I have this for consistency. > --- > arch/x86/kvm/emulate.c | 9 +++++++-- > arch/x86/kvm/kvm_cache_regs.h | 1 + > arch/x86/kvm/kvm_emulate.h | 1 + > arch/x86/kvm/svm/svm.c | 7 ++++++- > arch/x86/kvm/vmx/vmx.h | 9 ++++++++- > arch/x86/kvm/x86.c | 11 +++++++++++ > 6 files changed, 34 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c > index f9381a4055d6..ba3020e6f469 100644 > --- a/arch/x86/kvm/emulate.c > +++ b/arch/x86/kvm/emulate.c > @@ -4787,9 +4787,14 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, > return rc; > } > > -static inline bool emul_egpr_enabled(struct x86_emulate_ctxt *ctxt __maybe_unused) > +/* EGPR availability is controlled by the APX feature bit in XCR0. */ > +static inline bool emul_egpr_enabled(struct x86_emulate_ctxt *ctxt) > { > - return false; > + u64 xcr0; > + > + ctxt->ops->get_xcr(ctxt, XCR_XFEATURE_ENABLED_MASK, &xcr0); > + > + return xcr0 & XFEATURE_MASK_APX; > } > > int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type) > diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h > index 8ddb01191d6f..acdb3751317c 100644 > --- a/arch/x86/kvm/kvm_cache_regs.h > +++ b/arch/x86/kvm/kvm_cache_regs.h > @@ -3,6 +3,7 @@ > #define ASM_KVM_CACHE_REGS_H > > #include > +#include > > #define KVM_POSSIBLE_CR0_GUEST_BITS (X86_CR0_TS | X86_CR0_WP) > #define KVM_POSSIBLE_CR4_GUEST_BITS \ > diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h > index cc16211d61f6..673a82532c78 100644 > --- a/arch/x86/kvm/kvm_emulate.h > +++ b/arch/x86/kvm/kvm_emulate.h > @@ -237,6 +237,7 @@ struct x86_emulate_ops { > bool (*is_smm)(struct x86_emulate_ctxt *ctxt); > int (*leave_smm)(struct x86_emulate_ctxt *ctxt); > void (*triple_fault)(struct x86_emulate_ctxt *ctxt); > + int (*get_xcr)(struct x86_emulate_ctxt *ctxt, u32 index, u64 *xcr); > int (*set_xcr)(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr); > > gva_t (*get_untagged_addr)(struct x86_emulate_ctxt *ctxt, gva_t addr, > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c > index 3aa2c37754ef..e6a082686000 100644 > --- a/arch/x86/kvm/svm/svm.c > +++ b/arch/x86/kvm/svm/svm.c > @@ -5288,8 +5288,13 @@ static __init int svm_hardware_setup(void) > } > kvm_enable_efer_bits(EFER_NX); > > + /* > + * APX introduces EGPRs, which require additional VMCB support. > + * Disable APX until the necessary extensions are handled. > + */ > kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | > - XFEATURE_MASK_BNDCSR); > + XFEATURE_MASK_BNDCSR | > + XFEATURE_MASK_APX); > > if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) > kvm_enable_efer_bits(EFER_FFXSR); > diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h > index 6cf1eb739caf..784aa0504dce 100644 > --- a/arch/x86/kvm/vmx/vmx.h > +++ b/arch/x86/kvm/vmx/vmx.h > @@ -372,7 +372,14 @@ struct vmx_insn_info { > union insn_info info; > }; > > -static inline bool vmx_egpr_enabled(struct kvm_vcpu *vcpu __maybe_unused) { return false; } > +/* > + * EGPR availability is controlled by the APX xfeature bit in XCR0 and is > + * only accessible in 64-bit mode. > + */ > +static inline bool vmx_egpr_enabled(struct kvm_vcpu *vcpu) > +{ > + return vcpu->arch.xcr0 & XFEATURE_MASK_APX && is_64_bit_mode(vcpu); > +} > > static inline struct vmx_insn_info vmx_get_insn_info(struct kvm_vcpu *vcpu) > { > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 4c8c2fc3bda6..e087db0f4153 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -8843,6 +8843,16 @@ static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt) > kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt)); > } > > +static int emulator_get_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 *xcr) > +{ > + /* Only support XCR_XFEATURE_ENABLED_MASK now */ > + if (index != XCR_XFEATURE_ENABLED_MASK) > + return 1; > + > + *xcr = emul_to_vcpu(ctxt)->arch.xcr0; > + return 0; > +} > + > static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr) > { > return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr); > @@ -8915,6 +8925,7 @@ static const struct x86_emulate_ops emulate_ops = { > .is_smm = emulator_is_smm, > .leave_smm = emulator_leave_smm, > .triple_fault = emulator_triple_fault, > + .get_xcr = emulator_get_xcr, > .set_xcr = emulator_set_xcr, > .get_untagged_addr = emulator_get_untagged_addr, > .is_canonical_addr = emulator_is_canonical_addr,