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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fc73f7b8asm658082366b.27.2026.02.20.01.52.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 20 Feb 2026 01:52:06 -0800 (PST) Message-ID: Date: Fri, 20 Feb 2026 10:52:04 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7] crypto: qce - Add runtime PM and interconnect bandwidth scaling support To: quic_utiwari@quicinc.com, herbert@gondor.apana.org.au, thara.gopinath@gmail.com, davem@davemloft.net Cc: linux-crypto@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, quic_neersoni@quicinc.com References: <20260220072818.2921517-1-quic_utiwari@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260220072818.2921517-1-quic_utiwari@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: mEsfQKvaoI83Sh5Eb8WQNqgIIN4yY5Nb X-Authority-Analysis: v=2.4 cv=dqzWylg4 c=1 sm=1 tr=0 ts=69982ec8 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=COk6AnOGAAAA:8 a=KIb8oVNHrCvuKONrHFUA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIwMDA4NiBTYWx0ZWRfXxfwS8oATdS9d 4jE3+hiU0FuthuSYcBVrXv/jdNOa8BYswyYpyAvUvqO8yHvggHMdRaM3VhlZ3mezynfK6F59WSz N2JZQXPhrC9KtDsX0+K3mKuviv6a2zV6ct/cNdbQxPe24g2ecwGnwkz7fbmbIS0O1eZvHhrteuC Mi9RRvOi5S64dFFL+Y/lInyWlkIGtknaNmUEnGa5f8a5NZ7mkjryd73bULEtNN2zG5tqM5HPCdQ PEAiKMfHYvknhl+zcKfXRc//MS1Zrv1FU1hwbnui2iPcWMZpq/bQQM1Ls2+SzNu4PgIbpUYSlNb oWOZjEzt7EXVRsMDP+3h0W3/vQql8ULQJ1D9M1RpjLlBqx+Iv8WpS5THK7ziK44zFO6ETs3vQGo 0VAlo84VeZQ6agBD5NDpaUJuI7K/NmBfe/nZh1x6l/dMP0V0Obi3YmXwYhRFyP6RrEhF2VG+YKH CGN0sT4kfxv7E27HFIA== X-Proofpoint-GUID: mEsfQKvaoI83Sh5Eb8WQNqgIIN4yY5Nb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-20_01,2026-02-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602200086 On 2/20/26 8:28 AM, quic_utiwari@quicinc.com wrote: > From: Udit Tiwari > > The Qualcomm Crypto Engine (QCE) driver currently lacks support for > runtime power management (PM) and interconnect bandwidth control. > As a result, the hardware remains fully powered and clocks stay > enabled even when the device is idle. Additionally, static > interconnect bandwidth votes are held indefinitely, preventing the > system from reclaiming unused bandwidth. > > Address this by enabling runtime PM and dynamic interconnect > bandwidth scaling to allow the system to suspend the device when idle > and scale interconnect usage based on actual demand. Improve overall > system efficiency by reducing power usage and optimizing interconnect > resource allocation. [...] > +static int __maybe_unused qce_runtime_suspend(struct device *dev) I think you should be able to drop __maybe_unused if you drop the SET_ prefix in pm_ops and add a pm_ptr() around &qce_crypto_pm_ops in the assignment at the end > +{ > + struct qce_device *qce = dev_get_drvdata(dev); > + > + icc_disable(qce->mem_path); icc_disable() can also fail, since under the hood it's an icc_set(path, 0, 0), please check its retval > + > + return pm_clk_suspend(dev); > +} > + > +static int __maybe_unused qce_runtime_resume(struct device *dev) > +{ > + struct qce_device *qce = dev_get_drvdata(dev); > + int ret = 0; No need to initialize it here, as you overwrite this zero immediately a line below anyway > + > + ret = pm_clk_resume(dev); > + if (ret) > + return ret; > + > + ret = icc_set_bw(qce->mem_path, QCE_DEFAULT_MEM_BANDWIDTH, QCE_DEFAULT_MEM_BANDWIDTH); > + if (ret) > + goto err_icc; Normally I think bus votes are cast before clock re-enables to make sure the hw doesn't try to access a disabled bus path Konrad > + > + return 0; > + > +err_icc: > + pm_clk_suspend(dev); > + return ret; > +} > + > +static const struct dev_pm_ops qce_crypto_pm_ops = { > + SET_RUNTIME_PM_OPS(qce_runtime_suspend, qce_runtime_resume, NULL) > + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) > +}; > + > static const struct of_device_id qce_crypto_of_match[] = { > { .compatible = "qcom,crypto-v5.1", }, > { .compatible = "qcom,crypto-v5.4", }, > @@ -261,6 +323,7 @@ static struct platform_driver qce_crypto_driver = { > .driver = { > .name = KBUILD_MODNAME, > .of_match_table = qce_crypto_of_match, > + .pm = &qce_crypto_pm_ops, > }, > }; > module_platform_driver(qce_crypto_driver);