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Wed, 13 Aug 2025 11:08:20 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57DB8JOF015501 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Aug 2025 11:08:19 GMT Received: from [10.206.107.4] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 13 Aug 2025 04:08:14 -0700 Message-ID: Date: Wed, 13 Aug 2025 16:38:11 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Remove SDR104/SDR50 broken capabilities To: Krzysztof Kozlowski , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter CC: , , , , , , , , , , , References: <20250801084518.2259767-1-quic_sartgarg@quicinc.com> <20250801084518.2259767-5-quic_sartgarg@quicinc.com> <69f2807c-9a28-4b31-97cc-2756f0ab9fd4@kernel.org> <8b023e56-435b-43df-8b15-c562a494e06f@kernel.org> Content-Language: en-US From: Sarthak Garg In-Reply-To: <8b023e56-435b-43df-8b15-c562a494e06f@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CX22bScD_SV7lCuBYIpCB4sFzipBqTpI X-Proofpoint-ORIG-GUID: CX22bScD_SV7lCuBYIpCB4sFzipBqTpI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA2OCBTYWx0ZWRfX98xLFV266QbX m27GIrJhSGb85YleytGJ0sQtrACMSDLz2lJ9QoDSGFvL1IjUV8jzFpWDdwJ6Pf35WJ5HWUvIU7N yEppGUGTbYsYOFqHBCLPlynigAx0A3xSUKyh9BmYGe3ubhPVn3/mA2VFSTLtsUJYjG/WYMgteTP mjmuowFZxJB7ndNXUuWDGF8mi+RSurRoahyot3Pj257xkyj0Ivh8Ofq3QEkCoZX9wozlDmlwj/s 1zxKaTlg3P3EAg8efJvTzcx4WbHTp4whNwyfIxkvKHE8G/N+u1My3TrR5HENQsiBec/vLPB/WT9 yrK+K6Gu8YgkEjl8vcj8z66TM71mWqDUw+iZhR35AzeDyDsA7as6whxe7UHWhi8xdrtYzzdWVtq xyZ6Yizv X-Authority-Analysis: v=2.4 cv=YMafyQGx c=1 sm=1 tr=0 ts=689c7224 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=7vkX0yn46oB1UrFKko0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_01,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110068 On 8/5/2025 2:55 PM, Krzysztof Kozlowski wrote: > On 05/08/2025 11:19, Sarthak Garg wrote: >> >> >> On 8/1/2025 2:32 PM, Krzysztof Kozlowski wrote: >>> On 01/08/2025 10:45, Sarthak Garg wrote: >>>> The kernel now handles level shifter limitations affecting SD card >>>> modes, making it unnecessary to explicitly disable SDR104 and SDR50 >>>> capabilities in the device tree. >>>> >>>> However, due to board-specific hardware constraints particularly related >>>> to level shifter in this case the maximum frequency for SD High-Speed >>>> (HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD >>>> card in HS mode. This is achieved using the max-sd-hs-frequency property >>>> in the board DTS. >>>> >>>> Signed-off-by: Sarthak Garg >>>> --- >>>> arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 1 + >>>> arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 1 + >>>> arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 1 + >>>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 --- >>>> 4 files changed, 3 insertions(+), 3 deletions(-) >>>> >>> >>> This will break MMC for all of the users and nothing in commit msg or >>> cover letter explains that or mentions merging strategy. >>> >>> Exactly this case is covered by your internal guideline, no? Please read it. >>> >>> Best regards, >>> Krzysztof >> >> Just to make sure I’m addressing the right concern — are you primarily >> worried about the introduction of the max-sd-hs-frequency property in >> the board DTS files, or about the removal of the sdhci-caps-mask >> from the common sm8550.dtsi? > > > Apply this patch and test MMC. Does it work? No. Was it working? Yes. > > > Best regards, > Krzysztof You're absolutely right to raise the concern about potential breakage. After conducting additional testing across multiple boards, I’ve confirmed that the removal of SDR104/SDR50 broken capabilities does indeed affect V1 SM8550 devices. However, on V2 devices, all modes—including SDR104, SDR50, and HS—are fully functional and have been verified to work reliably. Based on your feedback, I will revise the patch to retain the broken SDR104/SDR50 capabilities in the common sm8550.dtsi, ensuring no impact on current sm8550 devices already in use. We will revisit the removal of broken capabilities dt property for upcoming targets after thorough validation and testing to ensure no regressions from the beginning. Please let me know if this approach aligns with your expectations. I’ll prepare and send out a revised patch accordingly. Best regards, Sarthak