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Wed, 16 Oct 2024 15:46:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGNLfX6rSgoFc/nbuaGHQPrn0ecbjygXBRhQu+9TrQF1OxT+t5t5C1LLK9R/zRxgCCHB6hMLA== X-Received: by 2002:a17:902:f60c:b0:20c:b0c7:7f0d with SMTP id d9443c01a7336-20d27ecadd6mr64931425ad.25.1729118789152; Wed, 16 Oct 2024 15:46:29 -0700 (PDT) Received: from [192.168.68.54] ([180.233.125.129]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-20d17f84e22sm33227695ad.52.2024.10.16.15.46.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Oct 2024 15:46:28 -0700 (PDT) Message-ID: Date: Thu, 17 Oct 2024 08:46:22 +1000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] KVM: arm64: Fix shift-out-of-bounds bug To: Ilkka Koskinen , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Akihiko Odaki Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org References: <20241016195755.65011-1-ilkka@os.amperecomputing.com> Content-Language: en-US From: Gavin Shan In-Reply-To: <20241016195755.65011-1-ilkka@os.amperecomputing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 10/17/24 5:57 AM, Ilkka Koskinen wrote: > Fix a shift-out-of-bounds bug reported by UBSAN when running > VM with MTE enabled host kernel. > > UBSAN: shift-out-of-bounds in arch/arm64/kvm/sys_regs.c:1988:14 > shift exponent 33 is too large for 32-bit type 'int' > CPU: 26 UID: 0 PID: 7629 Comm: qemu-kvm Not tainted 6.12.0-rc2 #34 > Hardware name: IEI NF5280R7/Mitchell MB, BIOS 00.00. 2024-10-12 09:28:54 10/14/2024 > Call trace: > dump_backtrace+0xa0/0x128 > show_stack+0x20/0x38 > dump_stack_lvl+0x74/0x90 > dump_stack+0x18/0x28 > __ubsan_handle_shift_out_of_bounds+0xf8/0x1e0 > reset_clidr+0x10c/0x1c8 > kvm_reset_sys_regs+0x50/0x1c8 > kvm_reset_vcpu+0xec/0x2b0 > __kvm_vcpu_set_target+0x84/0x158 > kvm_vcpu_set_target+0x138/0x168 > kvm_arch_vcpu_ioctl_vcpu_init+0x40/0x2b0 > kvm_arch_vcpu_ioctl+0x28c/0x4b8 > kvm_vcpu_ioctl+0x4bc/0x7a8 > __arm64_sys_ioctl+0xb4/0x100 > invoke_syscall+0x70/0x100 > el0_svc_common.constprop.0+0x48/0xf0 > do_el0_svc+0x24/0x38 > el0_svc+0x3c/0x158 > el0t_64_sync_handler+0x120/0x130 > el0t_64_sync+0x194/0x198 > > Fixes: 7af0c2534f4c ("KVM: arm64: Normalize cache configuration") > Cc: stable@vger.kernel.org > Signed-off-by: Ilkka Koskinen > --- > arch/arm64/kvm/sys_regs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Gavin Shan > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 375052d8cd22..665c576faba3 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1994,7 +1994,7 @@ static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > * one cache line. > */ > if (kvm_has_mte(vcpu->kvm)) > - clidr |= 2 << CLIDR_TTYPE_SHIFT(loc); > + clidr |= 2UL << CLIDR_TTYPE_SHIFT(loc); > Nit: It's more precise to have 2ULL since the type of @clidr is u64, equivalent to 'unsigned long long' on arm64. The pattern ULL has been used in reset_mpidr(). > __vcpu_sys_reg(vcpu, r->reg) = clidr; > Thanks, Gavin