From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D321FC6FA83 for ; Wed, 7 Sep 2022 07:47:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229811AbiIGHrB (ORCPT ); Wed, 7 Sep 2022 03:47:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230055AbiIGHqw (ORCPT ); Wed, 7 Sep 2022 03:46:52 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6048A61EC; Wed, 7 Sep 2022 00:46:48 -0700 (PDT) Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 701A96601EAA; Wed, 7 Sep 2022 08:46:45 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662536806; bh=5rRhUwtbnHMHj8qHNYZSNdWbtK8TwaDTS8b/kqMqOvs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=O5rA2NWcpnn9r/mL9r9xUO7jPxnXRDkPINVEd2L3Xe1Tg6yX183Dh939CKd+oPm20 vYwEVwc7QakrpFTonHl5AGB7FqpyMEu1HMALnDUuMUoOcFpPPqeiIJLkU4swguvkYX DDTqf2W5IY0SmY9NFsB8Xd/8bRdJag02T6dUWJsQ2/ZbWvcWZLihB8/ANzDo1K+DyN h60g2X+7BXuT6xwU+ZUHt1GC2spl2whKv/P4N1/pSZ0CZeQE/w+ZxD3PG6tIw3lcmd 57EiFNO3jl5MSiU9A21Q6zH9o5hiOj927wrKac+LsJH1LqFiyAmtgLzGloXq2JTqBj lJPnA1YvGlAkQ== Message-ID: Date: Wed, 7 Sep 2022 09:46:42 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents To: Chen-Yu Tsai Cc: matthias.bgg@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, miles.chen@mediatek.com, rex-bc.chen@mediatek.com, nfraprado@collabora.com, chun-jie.chen@mediatek.com, jose.exposito89@gmail.com, drinkcat@chromium.org, weiyi.lu@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org References: <20220905100416.42421-1-angelogioacchino.delregno@collabora.com> <20220905100416.42421-9-angelogioacchino.delregno@collabora.com> Content-Language: en-US From: AngeloGioacchino Del Regno In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Il 07/09/22 05:49, Chen-Yu Tsai ha scritto: > Hi, > > On Mon, Sep 5, 2022 at 6:04 PM AngeloGioacchino Del Regno > wrote: >> >> These PLLs are conflicting with GPU rates that can be generated by >> the GPU-dedicated MFGPLL and would require a special clock handler >> to be used, for very little and ignorable power consumption benefits. >> Also, we're in any case unable to set the rate of these PLLs to >> something else that is sensible for this task, so simply drop them: >> this will make the GPU to be clocked exclusively from MFGPLL for >> "fast" rates, while still achieving the right "safe" rate during >> PLL frequency locking. >> >> Signed-off-by: AngeloGioacchino Del Regno >> --- >> drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 -- >> 1 file changed, 2 deletions(-) >> >> diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c >> index 4dde23bece66..6ff610c101ae 100644 >> --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c >> +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c >> @@ -301,8 +301,6 @@ static const char * const ipu_if_parents[] = { >> static const char * const mfg_parents[] = { >> "clk26m", >> "mainpll_d5_d2", >> - "univpll_d6", >> - "univpll_d7" > > I'd just comment them out and leave a note about it. Or remove them but > leave a note. Removed code will not be obvious to others. And given this > is probably the only public documentation of the hardware, it'd be a shame > to lose evidence of it. > That's fair, I totally agree with you. I'll send a v2 that adds a comment on top of mfg_parents explaining the possible parents and why d6/d7 were left out. Thanks, Angelo