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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e On 11/3/2026 3:31 PM, Alessio Ferri wrote: > The BCM6362 integrates a WLAN macro on a dedicated bcma backplane. > CFE leaves the macro clock gated and in reset, the backplane is > a big-endian peripheral, and none of the cores has a wrapper: > gating and reset of ChipCommon and of the 802.11 core go through > per-core control registers in a separate WLAN control block. > > Add a host driver for it that: > > - maps the ChipCommon and WLAN control register blocks; > - enables the clock, cycles the WLAN and WLAN UBUS resets and runs the > macro enable sequence bcma touches the backplane; > - provides big-endian register and block I/O ops; > - emulates BCMA_IOCTL, BCMA_IOST, BCMA_RESET_CTL and BCMA_RESET_ST > on top of the per-core control registers. The PHY bits of > BCMA_IOST report what b43 needs to hear; > - sets the big_endian and wrapperless bus flags before scanning. > > As for the PCI and generic SoC hosts, the driver is linked into > bcma.ko and registered from bcma_modinit(). > > Add a MAINTAINERS entry for the driver and its binding. > > The 802.11 core (rev 0x16) is handled by b43 once a SPROM is > available; on this SoC it is not stored on the chip and has to be > provided. In openwrt i use 6362-sprom plus fixups. > > Signed-off-by: Alessio Ferri Very neat, with Philip's comment addressed: Reviewed-by: Florian Fainelli -- Florian