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Fri, 13 Mar 2026 05:21:56 -0700 (PDT) X-Received: by 2002:a17:903:1503:b0:2af:c7c:afbc with SMTP id d9443c01a7336-2af0c7cb19amr7816555ad.31.1773404515583; Fri, 13 Mar 2026 05:21:55 -0700 (PDT) Received: from hu-arakshit-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2aece7ed9cdsm22318995ad.60.2026.03.13.05.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Mar 2026 05:21:55 -0700 (PDT) Date: Fri, 13 Mar 2026 17:51:48 +0530 From: Abhinaba Rakshit To: Herbert Xu , "David S. Miller" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Manivannan Sadhasivam , "James E.J. Bottomley" , "Martin K. Petersen" , Neeraj Soni Cc: linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v7 0/3] Enable ICE clock scaling Message-ID: References: <20260302-enable-ufs-ice-clock-scaling-v7-0-669b96ecadd8@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260302-enable-ufs-ice-clock-scaling-v7-0-669b96ecadd8@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA5NyBTYWx0ZWRfX7I2LdpgIHJRe b/Z76I0PEV1zDkV9HVB0XmRMF4wWFMvoVId34PbU3QcxQarue1udHAzPkegd8IfYYgmpCOZub0r 20SX3uoyeW8MyBJf/9GSxGCIB3VR2EIVpkWA3THduBsfgmkPMOjauSBo/Xqh8444so/Gl4kWR2g 7/7+b3ZWCRCdN/PxfQFYLgaVsIagWvhUE1L+OrZSITx/Y7F8v9nPdbf6viUjxvJ7eMf9jyFr1Bq zF0DZi4ixKHRI5dz3dUQ6YPGFDwG9KLh2dQKV11yjWSGzPOROErtypq4Axb2fONzzF2UoMGOvOR NJunbf+Ff3VhT9ESPNcIoMRkZIz9Ijv2ehP6XmgRmAWj22tQ4mZePMGTIjkNiFhfkebH3xH1ihn gJala4KubY8ZGL/hEx++cXkC7Al9VLTHKRfToeGc1xng2akAkbGPhE7Qd0w+wcyqOItQcbofG34 ojM3BnEgccaiFxu4J9Q== X-Proofpoint-GUID: XxNjnFxl9YKrWEFUVmdcl3dHfEtv_0-3 X-Proofpoint-ORIG-GUID: XxNjnFxl9YKrWEFUVmdcl3dHfEtv_0-3 X-Authority-Analysis: v=2.4 cv=H+vWAuYi c=1 sm=1 tr=0 ts=69b40165 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=FNyBlpCuAAAA:8 a=EUspDBNiAAAA:8 a=nmp4smzA0mTOGrukFIAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=RlW-AWeGUCXs_Nkyno-6:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_02,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130097 On Mon, Mar 02, 2026 at 04:19:12PM +0530, Abhinaba Rakshit wrote: > Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine) > using the OPP framework. During ICE device probe, the driver now attempts to > parse an optional OPP table from the ICE-specific device tree node for > DVFS-aware operations. API qcom_ice_scale_clk is exposed by ICE driver > and is invoked by UFS host controller driver in response to clock scaling > requests, ensuring coordination between ICE and host controller. > > For MMC controllers that do not support clock scaling, the ICE clock frequency > is kept aligned with the MMC controller’s clock rate (TURBO) to ensure > consistent operation. > > Dynamic clock scaling based on OPP tables enables better power-performance > trade-offs. By adjusting ICE clock frequencies according to workload and power > constraints, the system can achieve higher throughput when needed and > reduce power consumption during idle or low-load conditions. > > The OPP table remains optional, absence of the table will not cause > probe failure. However, in the absence of an OPP table, ICE clocks will > remain at their default rates, which may limit performance under > high-load scenarios or prevent performance optimizations during idle periods. > > Merge Order and Dependencies > ============================ > > Patch 1/4 (dt-bindings) from the previous series > (https://lore.kernel.org/all/aaKt9PET6lVkBcif@gondor.apana.org.au/) has already > been applied. This v7 series therefore includes only the ICE driver and > UFS driver changes (previously patches 2–4). > > Patch 1 is the change which should be merged first. > > Patch 2 is dependent on patch 1 for the qcom_ice_scale_clk API to be available. > Patch 3 is dependent on patch 1 for opp-table parsing to be enabled in the > ICE driver. > > Patch 2 and patch 3 are *not* dependent on each other. Once patch 1 is > merged, patch (2,3) can be applied independently by their respective > maintainers. > > Signed-off-by: Abhinaba Rakshit > --- > Changes in v7: > - Replace the custom rounding flags with 'bool round_ceil' as suggested. > - Update the dev_info log-line. > - Dropped dt-bindings patch (already applied by in previous patchseries). > - Add merge order and dependencies as suggested. > - Link to v6: https://lore.kernel.org/r/20260219-enable-ufs-ice-clock-scaling-v6-0-0c5245117d45@oss.qualcomm.com > > Changes in v6: > - Remove scale_up parameter from qcom_ice_scale_clk API. > - Remove having max_freq and min_freq as the checks for overclocking and underclocking is no-longer needed. > - UFS driver passes rounding flags depending on scale_up value. > - Ensure UFS driver does not fail devfreq requests if ICE OPP is not supported. > - Link to v5: https://lore.kernel.org/r/3ecb8d08-64cb-4fe1-bebd-1532dc5a86af@oss.qualcomm.com > > Changes in v5: > - Update operating-points-v2 property in dtbindings as suggested. > - Fix comment styles. > - Add argument in qcom_ice_create to distinguish between legacy bindings and newer bindings. > - Ensure to drop votes in suspend and enable the last vote in resume. > - Link to v4: https://lore.kernel.org/r/20260128-enable-ufs-ice-clock-scaling-v4-0-260141e8fce6@oss.qualcomm.com > > Changes in v4: > - Enable multiple frequency scaling based OPP-entries as suggested in v3 patchset. > - Include bindings change: https://lore.kernel.org/all/20260123-add-operating-points-v2-property-for-qcom-ice-bindings-v1-1-2155f7aacc28@oss.qualcomm.com/. > - Link to v3: https://lore.kernel.org/r/20260123-enable-ufs-ice-clock-scaling-v3-0-d0d8532abd98@oss.qualcomm.com > > Changes in v3: > - Avoid clock scaling in case of legacy bindings as suggested. > - Use of_device_is_compatible to distinguish between legacy and non-legacy bindings. > - Link to v2: https://lore.kernel.org/r/20251121-enable-ufs-ice-clock-scaling-v2-0-66cb72998041@oss.qualcomm.com > > Changes in v2: > - Use OPP-table instead of freq-table-hz for clock scaling. > - Enable clock scaling for legacy targets as well, by fetching frequencies from storage opp-table. > - Introduce has_opp variable in qcom_ice structure to keep track, if ICE instance has dedicated OPP-table registered. > - Combined the changes for patch-series <20251001-set-ice-clock-to-turbo-v1-1-7b802cf61dda@oss.qualcomm.com> as suggested. > - Link to v1: https://lore.kernel.org/r/20251001-enable-ufs-ice-clock-scaling-v1-0-ec956160b696@oss.qualcomm.com > > --- > Abhinaba Rakshit (3): > soc: qcom: ice: Add OPP-based clock scaling support for ICE > ufs: host: Add ICE clock scaling during UFS clock changes > soc: qcom: ice: Set ICE clk to TURBO on probe > > drivers/soc/qcom/ice.c | 89 +++++++++++++++++++++++++++++++++++++++++++-- > drivers/ufs/host/ufs-qcom.c | 19 +++++++++- > include/soc/qcom/ice.h | 2 + > 3 files changed, 106 insertions(+), 4 deletions(-) > --- > base-commit: fe4d0dea039f2befb93f27569593ec209843b0f5 > change-id: 20251120-enable-ufs-ice-clock-scaling-b063caf3e6f9 > > Best regards, > -- > Abhinaba Rakshit Just a gentle reminder regarding this patch series. Whenever any maintainers got a chance, I’d appreciate a review. Please let me know, anything pending from myside. Abhinaba Rakshit