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Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.5.1 Subject: Re: [PATCH v2 1/2] dt-bindings: watchdog: Add NXP Software Watchdog Timer To: Daniel Lezcano , wim@linux-watchdog.org Cc: linux@roeck-us.net, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, S32@nxp.com, ghennadi.procopciuc@nxp.com, thomas.fossati@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Vincent Guittot References: <20250402154942.3645283-1-daniel.lezcano@linaro.org> <20250402154942.3645283-2-daniel.lezcano@linaro.org> <64b6d599-fe67-586a-e4b0-73d9b73499de@oss.nxp.com> <93d83df2-d3bc-e32d-70a6-158571504275@oss.nxp.com> <60132403-d849-47a7-a11c-e829ffefc7a9@linaro.org> Content-Language: en-US From: Ghennadi Procopciuc In-Reply-To: <60132403-d849-47a7-a11c-e829ffefc7a9@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: AM9P193CA0015.EURP193.PROD.OUTLOOK.COM (2603:10a6:20b:21e::20) To DU2PR04MB8582.eurprd04.prod.outlook.com (2603:10a6:10:2d9::24) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8582:EE_|PAXPR04MB8126:EE_ X-MS-Office365-Filtering-Correlation-Id: fade5ce0-59f0-4554-7a17-08dd75901b5b X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|7416014; 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>>>>> +        reg = <0x40100000 0x1000>; >>>>> +        clocks = <&clks 0x3a>; >>>>> +        timeout-sec = <10>; >>>>> +    }; >>>> >>>> The S32G reference manual specifies two clocks for the SWT module: one >>>> for the registers and another for the counter itself. Shouldn't both >>>> clocks be represented in the bindings? >>> >>> AFAICS, there are two clocks as described in the documentation for the >>> s32g2 page 846, section 23.7.3.3 SWT clocking. >> >> This diagram illustrates the module clocks and their connections to the >> S32GS system clocks. From the module's perspective, there are three >> clocks: MODULE_CLOCK, REG_INTF, and COUNTER_CLOCK. Specifically, on >> S32G2 SoCs, the first two are connected to XBAR_DIV3_CLK, while the >> counter clock is linked to FIRC_CLK. Based on my understanding of the >> device tree, this configuration should be listed as follows: >> >> clocks = <&clks XBAR_DIV3_CLK>, <&clks XBAR_DIV3_CLK>, <&clks FIRC_CLK>; >> clock-names = "module", "reg", "counter"; >> >> Configuring it this way allows flexibility to reuse the same clocking >> scheme for other SoCs where the integration is performed differently. It >> is possible that the 'module' and 'reg' clocks could be linked to two >> distinct system clocks. > > That is something we can handle when the other SoC will be in the > process of being upstream, no ? > > I don't see how that can help with the current hardware we are > describing. What is the benefit ? > The benefit is that the binding accurately describes the hardware module, and no changes are expected in this area over time, even if different integrations of the module are performed on other SoCs. Otherwise, the binding will contain a different set of clocks depending on the SoC integration, even though the exact same hardware IP is used. > I would prefer to stick to what is needed today > >>> The module and the register clock are fed by the XBAR_DIV3_CLK which is >>> an system clock always-on. >> >> XBAR_DIV3_CLK is not an always-on clock, meaning it is not available >> during suspend, if that is what you mean by always-on. The SIRC can be >> considered the only always-on clock on this device. >> >>> >>> The counter is fed by the FIRC_CLK which described as "FIRC_CLK is the >>> default clock for the entire system at power-up." >>> >>>  From my understanding, we should not describe the XBAR_DIV3_CLK as >>> it is >>> a system clock. >>> >>> And the FIRC_CLK is only there to get the clock rate in the driver. >>> >> > > -- Regards, Ghennadi