From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751519AbeA2Jqm (ORCPT ); Mon, 29 Jan 2018 04:46:42 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:47816 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750959AbeA2Jqk (ORCPT ); Mon, 29 Jan 2018 04:46:40 -0500 From: Yannick FERTRE To: Philippe CORNU , Benjamin Gaignard , Vincent ABRIOU , "David Airlie" , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , Archit Taneja , Andrzej Hajda , Laurent Pinchart CC: Fabien DESSENNE , Mickael REULIER , Ludovic BARRE , "Alexandre TORGUE" , Maxime Coquelin Subject: Re: [PATCH] drm/stm: ltdc: use crtc_mode_fixup to update adjusted_mode clock Thread-Topic: [PATCH] drm/stm: ltdc: use crtc_mode_fixup to update adjusted_mode clock Thread-Index: AQHTlfW5fhiVmJKoNU2zgLW/JMuSwKOKj1gA Date: Mon, 29 Jan 2018 09:46:21 +0000 Message-ID: References: <20180125160101.9102-1-philippe.cornu@st.com> In-Reply-To: <20180125160101.9102-1-philippe.cornu@st.com> Accept-Language: fr-FR, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.75.127.49] Content-Type: text/plain; charset="utf-8" Content-ID: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-01-29_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id w0T9kmGS024903 On 01/25/2018 05:01 PM, Philippe Cornu wrote: > There is a difference between the panel/bridge requested pixel clock > value and the real one due to the hw platform clock preciseness (pll, > dividers...). This patch updates the adjusted_mode clock value with > the real hw clock value so then attached encoder & connector can use > it for precise timing computations. Reviewed-by: Yannick Fertré > Signed-off-by: Philippe Cornu > --- > drivers/gpu/drm/stm/ltdc.c | 35 +++++++++++++++++++++++++---------- > 1 file changed, 25 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c > index b48589343ae1..90b3de516c91 100644 > --- a/drivers/gpu/drm/stm/ltdc.c > +++ b/drivers/gpu/drm/stm/ltdc.c > @@ -428,12 +428,35 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, > reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); > } > > +static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, > + const struct drm_display_mode *mode, > + struct drm_display_mode *adjusted_mode) > +{ > + struct ltdc_device *ldev = crtc_to_ltdc(crtc); > + int rate = mode->clock * 1000; > + > + /* > + * TODO clk_round_rate() does not work yet. When ready, it can > + * be used instead of clk_set_rate() then clk_get_rate(). > + */ > + > + clk_disable(ldev->pixel_clk); > + if (clk_set_rate(ldev->pixel_clk, rate) < 0) { > + DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); > + return false; > + } > + clk_enable(ldev->pixel_clk); > + > + adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; > + > + return true; > +} > + > static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) > { > struct ltdc_device *ldev = crtc_to_ltdc(crtc); > struct drm_display_mode *mode = &crtc->state->adjusted_mode; > struct videomode vm; > - int rate = mode->clock * 1000; > u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; > u32 total_width, total_height; > u32 val; > @@ -456,15 +479,6 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) > total_width = accum_act_w + vm.hfront_porch; > total_height = accum_act_h + vm.vfront_porch; > > - clk_disable(ldev->pixel_clk); > - > - if (clk_set_rate(ldev->pixel_clk, rate) < 0) { > - DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); > - return; > - } > - > - clk_enable(ldev->pixel_clk); > - > /* Configures the HS, VS, DE and PC polarities. Default Active Low */ > val = 0; > > @@ -528,6 +542,7 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, > } > > static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { > + .mode_fixup = ltdc_crtc_mode_fixup, > .mode_set_nofb = ltdc_crtc_mode_set_nofb, > .atomic_flush = ltdc_crtc_atomic_flush, > .atomic_enable = ltdc_crtc_atomic_enable,