Re: [PATCH v2 5/5] iio: adc: ad4130: add new supported parts

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Mon, Mar 16, 2026 at 08:45:45AM -0300, Jonathan Santos wrote:
> Add support for AD4129-4/8, AD4130-4, and AD4131-4/8 variants.
> 
> The AD4129 series supports the same FIFO interface as the AD4130 but with
> reduced resolution (16-bit). The AD4131 series lacks FIFO support, so
> triggered buffer functionality is introduced.
> 
> The 4-channel variants feature fewer analog inputs, GPIOs, and sparse pin
> mappings for VBIAS, analog inputs, and excitation currents. The driver now
> handles these differences with chip-specific configurations, including pin
> mappings and GPIO counts.

...


> +/* Map logical pins to register value */
> +static const u8 ad4130_4_pin_map[] = {
> +	0x00, /* AIN0/VBIAS_0 */
> +	0x01, /* AIN1/VBIAS_1 */
> +	0x04, /* AIN2/VBIAS_2 */
> +	0x05, /* AIN3/VBIAS_3 */
> +	0x0A, /* AIN4/VBIAS_4 */
> +	0x0B, /* AIN5/VBIAS_5 */
> +	0x0E, /* AIN6/VBIAS_6 */
> +	0x0F, /* AIN7/VBIAS_7 */
> +};
> +
> +/* Pin mapping for AIN0..AIN15, VBIAS_0..VBIAS_15 */

Perhaps making the above also consistent with this?

/* Pin mapping for AIN0..AIN7, VBIAS_0..VBIAS_7 */
static const u8 ad4130_4_pin_map[] = {
	0x00, 0x01, 0x04, 0x05, 0x0A, 0x0B, 0x0E, 0x0F, /* 0 - 7 */
};


> +static const u8 ad4130_8_pin_map[] = {
> +	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 0 - 7 */
> +	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, /* 8 - 15 */
> +};

-- 
With Best Regards,
Andy Shevchenko