From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
To: Thomas Gleixner <tglx@linutronix.de>,
LKML <linux-kernel@vger.kernel.org>
Cc: Michael Jeanson <mjeanson@efficios.com>,
Jens Axboe <axboe@kernel.dk>,
Peter Zijlstra <peterz@infradead.org>,
"Paul E. McKenney" <paulmck@kernel.org>,
Boqun Feng <boqun.feng@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
Wei Liu <wei.liu@kernel.org>, Dexuan Cui <decui@microsoft.com>,
x86@kernel.org, Arnd Bergmann <arnd@arndb.de>,
Heiko Carstens <hca@linux.ibm.com>,
Christian Borntraeger <borntraeger@linux.ibm.com>,
Sven Schnelle <svens@linux.ibm.com>,
Huacai Chen <chenhuacai@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [patch V4 14/36] rseq: Cache CPU ID and MM CID values
Date: Tue, 9 Sep 2025 09:43:58 -0400 [thread overview]
Message-ID: <ac375e1e-87a6-43ab-8f2c-7d9ab4f2f34d@efficios.com> (raw)
In-Reply-To: <20250908212926.161186107@linutronix.de>
On 2025-09-08 17:31, Thomas Gleixner wrote:
> In preparation for rewriting RSEQ exit to user space handling provide
> storage to cache the CPU ID and MM CID values which were written to user
> space. That prepares for a quick check, which avoids the update when
> nothing changed.
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
>
> ---
> include/linux/rseq.h | 7 +++++--
> include/linux/rseq_types.h | 21 +++++++++++++++++++++
> include/trace/events/rseq.h | 4 ++--
> kernel/rseq.c | 4 ++++
> 4 files changed, 32 insertions(+), 4 deletions(-)
>
> --- a/include/linux/rseq.h
> +++ b/include/linux/rseq.h
> @@ -57,6 +57,7 @@ static inline void rseq_virt_userspace_e
> static inline void rseq_reset(struct task_struct *t)
> {
> memset(&t->rseq, 0, sizeof(t->rseq));
> + t->rseq.ids.cpu_cid = ~0ULL;
> }
>
> static inline void rseq_execve(struct task_struct *t)
> @@ -70,10 +71,12 @@ static inline void rseq_execve(struct ta
> */
> static inline void rseq_fork(struct task_struct *t, unsigned long clone_flags)
> {
> - if (clone_flags & CLONE_VM)
> + if (clone_flags & CLONE_VM) {
> rseq_reset(t);
> - else
> + } else {
> t->rseq = current->rseq;
> + t->rseq.ids.cpu_cid = ~0ULL;
> + }
> }
>
> #else /* CONFIG_RSEQ */
> --- a/include/linux/rseq_types.h
> +++ b/include/linux/rseq_types.h
> @@ -31,17 +31,38 @@ struct rseq_event {
> };
>
> /**
> + * struct rseq_ids - Cache for ids, which need to be updated
need -> needs
> + * @cpu_cid: Compound of @cpu_id and @mm_cid to make the
> + * compiler emit a single compare on 64-bit
> + * @cpu_id: The CPU ID which was written last to user space
> + * @mm_cid: The MM CID which was written last to user space
> + *
> + * @cpu_id and @mm_cid are updated when the data is written to user space.
> + */
> +struct rseq_ids {
> + union {
> + u64 cpu_cid;
> + struct {
> + u32 cpu_id;
> + u32 mm_cid;
> + };
> + };
> +};
> +
> +/**
> * struct rseq_data - Storage for all rseq related data
> * @usrptr: Pointer to the registered user space RSEQ memory
> * @len: Length of the RSEQ region
> * @sig: Signature of critial section abort IPs
> * @event: Storage for event management
> + * @ids: Storage for cached CPU ID and MM CID
It's far from clear from the diff, but is there a missing space at the
beginning of the line above ?
Other than that:
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
> */
> struct rseq_data {
> struct rseq __user *usrptr;
> u32 len;
> u32 sig;
> struct rseq_event event;
> + struct rseq_ids ids;
> };
>
> #else /* CONFIG_RSEQ */
> --- a/include/trace/events/rseq.h
> +++ b/include/trace/events/rseq.h
> @@ -21,9 +21,9 @@ TRACE_EVENT(rseq_update,
> ),
>
> TP_fast_assign(
> - __entry->cpu_id = raw_smp_processor_id();
> + __entry->cpu_id = t->rseq.ids.cpu_id;
> __entry->node_id = cpu_to_node(__entry->cpu_id);
> - __entry->mm_cid = task_mm_cid(t);
> + __entry->mm_cid = t->rseq.ids.mm_cid;
> ),
>
> TP_printk("cpu_id=%d node_id=%d mm_cid=%d", __entry->cpu_id,
> --- a/kernel/rseq.c
> +++ b/kernel/rseq.c
> @@ -184,6 +184,10 @@ static int rseq_update_cpu_node_id(struc
> rseq_unsafe_put_user(t, node_id, node_id, efault_end);
> rseq_unsafe_put_user(t, mm_cid, mm_cid, efault_end);
>
> + /* Cache the user space values */
> + t->rseq.ids.cpu_id = cpu_id;
> + t->rseq.ids.mm_cid = mm_cid;
> +
> /*
> * Additional feature fields added after ORIG_RSEQ_SIZE
> * need to be conditionally updated only if
>
--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com
next prev parent reply other threads:[~2025-09-09 13:44 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 21:31 [patch V4 00/36] rseq: Optimize exit to user space Thomas Gleixner
2025-09-08 21:31 ` [patch V4 01/36] rseq: Avoid pointless evaluation in __rseq_notify_resume() Thomas Gleixner
2025-09-08 21:31 ` [patch V4 02/36] rseq: Condense the inline stubs Thomas Gleixner
2025-09-08 21:31 ` [patch V4 03/36] rseq: Move algorithm comment to top Thomas Gleixner
2025-09-08 21:31 ` [patch V4 04/36] rseq: Remove the ksig argument from rseq_handle_notify_resume() Thomas Gleixner
2025-09-08 21:31 ` [patch V4 05/36] rseq: Simplify registration Thomas Gleixner
2025-09-08 21:31 ` [patch V4 06/36] rseq: Simplify the event notification Thomas Gleixner
2025-09-09 13:18 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 07/36] rseq, virt: Retrigger RSEQ after vcpu_run() Thomas Gleixner
2025-09-09 0:00 ` Sean Christopherson
2025-09-09 12:10 ` Thomas Gleixner
2025-09-09 13:21 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 08/36] rseq: Avoid CPU/MM CID updates when no event pending Thomas Gleixner
2025-09-09 13:25 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 09/36] rseq: Introduce struct rseq_data Thomas Gleixner
2025-09-09 13:30 ` Mathieu Desnoyers
2025-09-12 20:44 ` Thomas Gleixner
2025-09-12 21:33 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 10/36] entry: Cleanup header Thomas Gleixner
2025-09-08 21:31 ` [patch V4 11/36] entry: Remove syscall_enter_from_user_mode_prepare() Thomas Gleixner
2025-09-09 13:33 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 12/36] entry: Inline irqentry_enter/exit_from/to_user_mode() Thomas Gleixner
2025-09-09 13:38 ` Mathieu Desnoyers
2025-09-09 14:10 ` Thomas Gleixner
2025-09-09 14:59 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 13/36] sched: Move MM CID related functions to sched.h Thomas Gleixner
2025-09-08 21:31 ` [patch V4 14/36] rseq: Cache CPU ID and MM CID values Thomas Gleixner
2025-09-09 13:43 ` Mathieu Desnoyers [this message]
2025-09-09 14:13 ` Thomas Gleixner
2025-09-09 15:01 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 15/36] rseq: Record interrupt from user space Thomas Gleixner
2025-09-09 13:53 ` Mathieu Desnoyers
2025-09-09 14:17 ` Thomas Gleixner
2025-09-09 15:05 ` Mathieu Desnoyers
2025-09-08 21:31 ` [patch V4 16/36] rseq: Provide tracepoint wrappers for inline code Thomas Gleixner
2025-09-08 21:31 ` [patch V4 17/36] rseq: Expose lightweight statistics in debugfs Thomas Gleixner
2025-09-08 21:32 ` [patch V4 18/36] rseq: Provide static branch for runtime debugging Thomas Gleixner
2025-09-08 21:32 ` [patch V4 19/36] rseq: Provide and use rseq_update_user_cs() Thomas Gleixner
2025-09-09 15:11 ` Mathieu Desnoyers
2025-09-08 21:32 ` [patch V4 20/36] rseq: Replace the original debug implementation Thomas Gleixner
2025-09-08 21:32 ` [patch V4 21/36] rseq: Make exit debugging static branch based Thomas Gleixner
2025-09-08 21:32 ` [patch V4 22/36] rseq: Use static branch for syscall exit debug when GENERIC_IRQ_ENTRY=y Thomas Gleixner
2025-09-08 21:32 ` [patch V4 23/36] rseq: Provide and use rseq_set_ids() Thomas Gleixner
2025-09-11 13:40 ` Mathieu Desnoyers
2025-09-11 16:02 ` Thomas Gleixner
2025-09-11 17:13 ` Mathieu Desnoyers
2025-09-08 21:32 ` [patch V4 24/36] rseq: Separate the signal delivery path Thomas Gleixner
2025-09-08 21:32 ` [patch V4 25/36] rseq: Rework the TIF_NOTIFY handler Thomas Gleixner
2025-09-08 21:32 ` [patch V4 26/36] rseq: Optimize event setting Thomas Gleixner
2025-09-11 14:03 ` Mathieu Desnoyers
2025-09-11 16:06 ` Thomas Gleixner
2025-09-11 17:15 ` Mathieu Desnoyers
2025-09-12 6:58 ` Thomas Gleixner
2025-09-08 21:32 ` [patch V4 27/36] rseq: Implement fast path for exit to user Thomas Gleixner
2025-09-11 14:27 ` Mathieu Desnoyers
2025-09-11 16:08 ` Thomas Gleixner
2025-09-08 21:32 ` [patch V4 28/36] rseq: Switch to fast path processing on " Thomas Gleixner
2025-09-11 14:44 ` Mathieu Desnoyers
2025-09-11 14:45 ` Mathieu Desnoyers
2025-09-11 16:50 ` Thomas Gleixner
2025-09-11 16:47 ` Thomas Gleixner
2025-09-11 20:00 ` Mathieu Desnoyers
2025-09-12 14:22 ` Thomas Gleixner
2025-09-12 15:44 ` Mathieu Desnoyers
2025-09-08 21:32 ` [patch V4 29/36] entry: Split up exit_to_user_mode_prepare() Thomas Gleixner
2025-09-08 21:32 ` [patch V4 30/36] rseq: Split up rseq_exit_to_user_mode() Thomas Gleixner
2025-09-08 21:32 ` [patch V4 31/36] asm-generic: Provide generic TIF infrastructure Thomas Gleixner
2025-09-17 6:16 ` [tip: core/core] " tip-bot2 for Thomas Gleixner
2025-09-08 21:32 ` [patch V4 32/36] x86: Use generic TIF bits Thomas Gleixner
2025-09-17 6:16 ` [tip: core/core] " tip-bot2 for Thomas Gleixner
2025-09-08 21:32 ` [patch V4 33/36] s390: " Thomas Gleixner
2025-09-11 9:11 ` Sven Schnelle
2025-09-11 11:03 ` Heiko Carstens
2025-09-17 6:16 ` [tip: core/core] " tip-bot2 for Thomas Gleixner
2025-09-08 21:32 ` [patch V4 34/36] loongarch: " Thomas Gleixner
2025-09-17 6:16 ` [tip: core/core] " tip-bot2 for Thomas Gleixner
2025-09-08 21:32 ` [patch V4 35/36] riscv: " Thomas Gleixner
2025-09-17 6:16 ` [tip: core/core] " tip-bot2 for Thomas Gleixner
2025-09-08 21:32 ` [patch V4 36/36] rseq: Switch to TIF_RSEQ if supported Thomas Gleixner
2025-09-10 13:55 ` [patch V4 00/36] rseq: Optimize exit to user space Jens Axboe
2025-09-10 14:45 ` Michael Jeanson
2025-09-10 15:34 ` Jens Axboe
2025-09-10 14:54 ` Thomas Gleixner
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