Re: [PATCH v2] ACPI: RISC-V: CPPC: Implement cpc_read_ffh_fb_ctrs()

[Jie Zhan <zhanjie9@hisilicon.com>]

On 9/9/2026 3:15 PM, Yufan Dou wrote:
> On RISC-V, reading FFH feedback counters on a remote hart through
> cpc_read_ffh() requires a separate IPI for each register.
> cppc_get_perf_ctrs() therefore samples the delivered and reference
> counters in two separate IPIs. Variation in the delay between these
> reads distorts the delivered/reference ratio and thus the frequency
> reported by cpufreq.
> 
> Implement cpc_read_ffh_fb_ctrs() to read both counters back-to-back
> in a single callback on the target hart. For remote reads, this
> reduces two IPIs to one and narrows the separation between the
> counter samples. Support CSR-type, SBI-type and mixed-type pairs.
> Pairing SBI reads does not reduce the number of SBI calls, but
> still avoids a separate IPI for each counter.
> 
> Factor the execution-context handling into cppc_ffh_read_on_cpu(),
> shared by cpc_read_ffh() and cpc_read_ffh_fb_ctrs(). CPPC frequency
> invariance (FIE) reads non-PCC counters directly from the scheduler
> tick, with local interrupts disabled. Unconditionally rejecting
> such reads prevents the frequency scale from being updated.
> 
> Following arm64's counters_read_on_cpu(), invoke the callback
> directly when interrupts are disabled and the target is the current
> CPU. Reject remote reads in that context. Otherwise, use
> smp_call_function_single() and propagate its return value before
> accessing the callback results.
> 
> Frequency accuracy testing used CSR-type delivered and reference
> counters, with CPU1 kept busy by:
> 
>   # stress-ng --cpu 1 --taskset 1
> 
> On a CPU with cpuinfo_max_freq of 3000000 kHz:
> 
> Before:
> 
>   Maximum observed cpuinfo_cur_freq: 3201369 kHz
>   Maximum observed deviation:        +201369 kHz (+6.71%)
> 
> After:
> 
>   Maximum observed cpuinfo_cur_freq: 3009646 kHz
>   Maximum observed deviation:          +9646 kHz (+0.32%)
> 
> The maximum observed deviation from cpuinfo_max_freq decreased
> by 95.2%.
> 
> Additional testing covered the CPPC FIE tick path and SBI-type
> FFH register reads.
> 
> Co-developed-by: Yicong Yang <yang.yicong@picoheart.com>
> Signed-off-by: Yicong Yang <yang.yicong@picoheart.com>
> Signed-off-by: Yufan Dou <douyufan@picoheart.com>
> Reviewed-by: Sunil V L <sunilvl@oss.qualcomm.com>
LGTM, thanks!
Reviewed-by: Jie Zhan <zhanjie9@hisilicon.com> 
> ---
> Changes in v2:
> - Support SBI-type and mixed-type counter pairs in a single callback
>   on the target hart, reducing remote reads to one IPI.
> - Factor out cppc_ffh_read_on_cpu() for both FFH read interfaces.
>   Allow local reads with interrupts disabled and reject remote reads
>   in that context, following arm64's counters_read_on_cpu().
> - Propagate synchronous cross-CPU call errors in cpc_read_ffh().
> - Test the CPPC FIE tick path and SBI-type FFH register reads.
> 
> v1:
> https://lore.kernel.org/all/20260902083450.2348-1-douyufan@picoheart.com/
> 
>  drivers/acpi/riscv/cppc.c | 102 ++++++++++++++++++++++++++++++++++++--
>  1 file changed, 97 insertions(+), 5 deletions(-)
> 
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