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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca792f3f54sm1386123eec.7.2026.04.01.21.08.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 21:08:59 -0700 (PDT) Date: Wed, 1 Apr 2026 21:08:57 -0700 From: Qiang Yu To: Krzysztof Kozlowski Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , johan@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 1/4] dt-bindings: clock: qcom,sm8550-tcsr: Add QREF regulator supplies for glymur Message-ID: References: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com> <20260331-qref_vote-v1-1-3fd7fbf87864@oss.qualcomm.com> <6d0c1154-b249-4c44-acb4-52d43d626fa6@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6d0c1154-b249-4c44-acb4-52d43d626fa6@kernel.org> X-Authority-Analysis: v=2.4 cv=L90QguT8 c=1 sm=1 tr=0 ts=69cdebdd cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=V3kEKwUAXSpzXU6G4ikA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-ORIG-GUID: Znldj-PXWWnjEJP3I8H_4c9Kk3CxxRRI X-Proofpoint-GUID: Znldj-PXWWnjEJP3I8H_4c9Kk3CxxRRI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAyMDAzMyBTYWx0ZWRfXy8fhFc3QEhD0 eTX6vPu4LOQUe6onbPslrpKdrfR4icLx1+sF4RHIc/o8NBoIIkA9N85PweRP08l4rxnBXxC3Jl1 1fjOKalyNnUl5F/abH2mrieuVYPBPuuj/BYDO8UdQkvPcdllTDXSgg+SApleQJ68ihpqG2upUXA S55eq/vxmaaWiZCppk14r9EV9yvQXe3fdazwqDySLizhm9arkdF9ZAh3kMM5PEYCwjeTKbrtvyn MqmvWmMue2vXFOmLtqzOCYTtPaV0mB/6qK7duvtIE/WE7I6ewrw1SSyh84iGwQJh/XsvWKLOuA4 q3V3Ei9l2ad5B1aI+2zvZcXKyMiCYllF2DqRTZOC9MoFChF41JgCK+VciYFhO4X6kDo5kTNlMqo zTqzE3DmCsqmajbq5s8DQEYA0QNE++tYJ4Tq9E92FEt5QkTwo5glOpYKjYuZR2ru7K/ipV4kcAC bts9qaLWboJBguc2ymA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-02_01,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 priorityscore=1501 spamscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604020033 On Wed, Apr 01, 2026 at 09:18:12AM +0200, Krzysztof Kozlowski wrote: > On 01/04/2026 08:35, Qiang Yu wrote: > > The glymur TCSR PCIe clkref clocks require regulator supplies for the > > QREF block and its refgen reference voltage generator. Add the optional > > supply properties restricted to qcom,glymur-tcsr via an allOf/if/then > > conditional schema. > > > > Switch from additionalProperties to unevaluatedProperties so that > > properties defined inside the if/then block are correctly recognised as > > evaluated and not rejected by the schema validator. > > Sorry, but no. There is a reason for that why additionalProperties fail > and writing-bindings explain that. > Okay, will change this part. > > > > Signed-off-by: Qiang Yu > > --- > > .../bindings/clock/qcom,sm8550-tcsr.yaml | 26 +++++++++++++++++++++- > > 1 file changed, 25 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > > index ae9aef0e54e8b8b85bc70e6096d524447091f39e..88db650e69ef2388a5bfb6783a57c1d48c0e780f 100644 > > --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml > > @@ -49,11 +49,35 @@ properties: > > '#reset-cells': > > const: 1 > > > > +allOf: > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: qcom,glymur-tcsr > > + then: > > + properties: > > + vdda-refgen-0p9-supply: true > > + vdda-refgen-1p2-supply: true > > + vdda-qrefrx0-0p9-supply: true > > + vdda-qrefrx1-0p9-supply: true > > + vdda-qrefrx2-0p9-supply: true > > + vdda-qrefrx4-0p9-supply: true > > + vdda-qrefrx5-0p9-supply: true > > + vdda-qreftx0-0p9-supply: true > > + vdda-qreftx0-1p2-supply: true > > + vdda-qreftx1-0p9-supply: true > > + vdda-qrefrpt0-0p9-supply: true > > + vdda-qrefrpt1-0p9-supply: true > > + vdda-qrefrpt2-0p9-supply: true > > + vdda-qrefrpt3-0p9-supply: true > > + vdda-qrefrpt4-0p9-supply: true > > I really doubt that TCSR, which is a small, tiny tiny block the in SoC > have this ~15 pin supplies. > > Anyway, if it has, then device is quite different and should live in its > own schema. TX/RPT/RX are common QREF components across platforms; what changes by SoC is the number of instances and the routing topology. For example, a single PCIe path on Glymur and Kaanapali: - Glymur: CXO -> TX0 -> RPT0 -> RPT1 -> RPT2 -> RX2 -> PCIe4_PHY - Kaanapali: CXO -> TX0 -> RPT0 -> RPT1 -> RX0 -> PCIe0_PHY The DT supplies added in this series (vdda-qreftx*, vdda-qrefrpt* vdda-qrefrx*) supply to these TX/RPT/RX components and can be resused by other plarforms. - Qiang Yu