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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=CZ4I5Krl c=1 sm=1 tr=0 ts=688244ca cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=pSIa2sKh8ADkebnh61Ypzg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=KKAkSRfTAAAA:8 a=1B6o04Z4kyHWbw-D5gsA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: mVSMip9M0QnuIfv8XSfpjUm-kDBwTIF_ X-Proofpoint-GUID: mVSMip9M0QnuIfv8XSfpjUm-kDBwTIF_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI0MDExMSBTYWx0ZWRfXzdWIuRvZx2cV 7FFyxqE0flhhbvVjv/QqexCGC+qrDh6VFxmeP+gPb3rmLZN3o2ztzYMMUfjpuk0JbBxIWytW0uN 1FNnUV9tkalKarpIsh1oN8obLvQivtmUQM8282Ed/93JVwYRWZ9e3Mb62iIHJWio9QNKp2pw7cT UyrQfUC/nDHqfr7N+BwSrAgDGVeq+ySkWcaVKu+09uH5JfKMKaDpkxqJx/7VYULM+KNnaz20rPh Repo/Ux/qabLKI+OjP7jD/nxpm2cNTI1+Fa6X7eSsa8UVnTiIkKARXhEjnn3aMkZ74jeOV72QD+ WzdlIsDz3V/jmb9sINt4DeGxTU2dDokJIMd5ANie+yOThdhDhMT2t47Rv3P03TJTZ91Gfhg63QE IPz53cKDs07DeCEtUzCr9ThOBDHGFDiDwFvq6wXy2BcGOvMPrZybwZUgy06h2xAS0gbVUgVF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-24_02,2025-07-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507240111 On 7/21/2025 6:05 PM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along > the Frequency and Power Domain level, but by default we leave the > OPP core scale the interconnect ddr path. > > Declare the Bus Control Modules (BCMs) and the corresponding parameters > in the GPU info struct to allow the GMU to vote for the bandwidth. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..b313505e665ba50e46f2c2b7c34925b929a94c31 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c > @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { > .pwrup_reglist = &a7xx_pwrup_reglist, > .gmu_chipid = 0x7050001, > .gmu_cgc_mode = 0x00020202, > + .bcms = (const struct a6xx_bcm[]) { > + { .name = "SH0", .buswidth = 16 }, > + { .name = "MC0", .buswidth = 4 }, > + { > + .name = "ACV", > + .fixed = true, > + .perfmode = BIT(2), > + .perfmode_bw = 10687500, This configurations should be similar to X1-45. -Akhil > + }, > + { /* sentinel */ }, > + }, > }, > .preempt_record_size = 4192 * SZ_1K, > .speedbins = ADRENO_SPEEDBINS( > > --- > base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d > change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3 > > Best regards,