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Wed, 8 Jan 2020 18:41:03 +0000 Subject: Re: [PATCH v2] KVM: SVM: Override default MMIO mask if memory encryption is enabled From: Tom Lendacky To: Sean Christopherson Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Paolo Bonzini , Vitaly Kuznetsov , Wanpeng Li , Jim Mattson , Joerg Roedel , Brijesh Singh References: <20200106224931.GB12879@linux.intel.com> <20200106233846.GC12879@linux.intel.com> <20200107222813.GB16987@linux.intel.com> <298352c6-7670-2929-9621-1124775bfaed@amd.com> <20200107233102.GC16987@linux.intel.com> <20200108000412.GE16987@linux.intel.com> Message-ID: Date: Wed, 8 Jan 2020 12:41:01 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN6PR05CA0035.namprd05.prod.outlook.com (2603:10b6:805:de::48) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 Received: from [10.236.30.74] (165.204.77.1) by SN6PR05CA0035.namprd05.prod.outlook.com (2603:10b6:805:de::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.4 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: PeBa+kZPFPdbd0U8t1BwfcCw66z+80VheC4zLznQE6lcxiCIAoabeY0EPJDwOeuQMQGR5ewh0hhD1dg9fDqU0faLINJDG/FatB5zhhO5LYm8wtysr3xjlQmF2oMEQUyuqV80xzUhA18X5okLbme5aJJrg13XuyXKS8Yxy5l2SRMFtmKMHNnwpqygvyKj4x2O4e9YQ6ekrKtLy9N7MKZCk4LVTmShsCKWefLBGIobZ/d2FrZdYKBOFj2oaxXUdbayNBAUllb5C3gqwIKklEMrdzNv+COAeguqnvJ++ptZT4F4IKOoJd1TOO+EQxJpN8ABu795Gmi21dmFowHqOHV7BE70uoRpji2rd6+7+b739bs0Jby6E4Y+FlvoCdF+6GspgB2ZcaHLJqZayCZj3Bq5Og/dgI6v79PgVAI9EkeGza1pt+mx8Gzh8ocPKPZM3ObA X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 14b43a1a-e11a-40b2-af32-08d7946a5075 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jan 2020 18:41:03.6736 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Gq765lgufZm3zZ/73EgU+MhnCNGGj4+aHFBeQvuOuLqaN/I+TJdP2JvWhDVTz9XCmp45zcnhbbFNK+RWKBzkGQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3179 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/8/20 7:57 AM, Tom Lendacky wrote: > On 1/7/20 6:04 PM, Sean Christopherson wrote: >> On Tue, Jan 07, 2020 at 05:51:51PM -0600, Tom Lendacky wrote: >>> On 1/7/20 5:31 PM, Sean Christopherson wrote: >>>> AIUI, using phys_bits=48, then the standard scenario is Cbit=47 and some >>>> additional bits 46:M are reserved. Applying that logic to phys_bits=52, >>>> then Cbit=51 and bits 50:M are reserved, so there's a collision but it's >>> >>> There's no requirement that the C-bit correspond to phys_bits. So, for >>> example, you can have C-bit=51 and phys_bits=48 and so 47:M are reserved. >> >> But then using blindly using x86_phys_bits would break if the PA bits >> aren't reduced, e.g. C-bit=47 and phys_bits=47. AFAICT, there's no >> requirement that there be reduced PA bits when there is a C-bit. I'm >> guessing there aren't plans to ship such CPUs, but I don't see anything >> in the APM to prevent such a scenario. > > I can add in extra checks to see if C-bit == phys_bits, etc. and adjust > with appropriate limit checking. It's in the init path, so the extra > checks aren't a big deal. Just sent V3 of the patch. I believe I have all the areas we discussed covered. I also went back to using rsvd_bits() as was used before the L1TF changes. Let me know what you think. Thanks, Tom > > Thanks, > Tom > >> >> Maybe the least painful approach would be to go with a version of this >> patch and add a check that there are indeeded reserved/reduced bits? >> Probably with a WARN_ON_ONCE if the check fails. >>