From: Alison Schofield <alison.schofield@intel.com>
To: Li Ming <ming.li@zohomail.com>
Cc: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders
Date: Sun, 22 Mar 2026 19:39:45 -0700 [thread overview]
Message-ID: <acCn8Z_rmpbz3qdm@aschofie-mobl2.lan> (raw)
In-Reply-To: <20260321061459.1910205-1-ming.li@zohomail.com>
On Sat, Mar 21, 2026 at 02:14:59PM +0800, Li Ming wrote:
> Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can
> support 32 HDM decoders. Current implementation misses some decoders on
> CXL host bridge and switch in the case that the value of Decoder Count
> field in CXL HDM decoder Capability Register is greater than or equal to
> 9.
>
> Update calculation implementation to ensure the decoder count calculation
> is correct for CXL host bridge/switch ports.
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
next prev parent reply other threads:[~2026-03-23 2:40 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-21 6:14 Li Ming
2026-03-23 2:39 ` Alison Schofield [this message]
2026-03-23 15:37 ` Dave Jiang
2026-03-23 15:55 ` Gregory Price
2026-04-10 8:17 ` Li Ming
2026-04-10 18:39 ` Dave Jiang
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