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Thu, 22 Jan 2026 00:56:02 -0800 (PST) X-Received: by 2002:a05:6a00:1804:b0:81f:37b2:5657 with SMTP id d2e1a72fcca58-81f9f6abac6mr16169123b3a.17.1769072161927; Thu, 22 Jan 2026 00:56:01 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-81fa12b51fcsm17343898b3a.68.2026.01.22.00.55.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jan 2026 00:56:01 -0800 (PST) Message-ID: Date: Thu, 22 Jan 2026 14:25:53 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] PCI: dwc: Add support for retaining link during host init To: Bjorn Helgaas Cc: Vinod Koul , Neil Armstrong , Philipp Zabel , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260109155350.GA546142@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20260109155350.GA546142@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 1KK3wAeVqdL8Bxl6HAcMVeGhZubWhFQl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDA2MCBTYWx0ZWRfXwu/OajU5y6SU Ad2S2Kmh2eus6moSHArfN4ThDMW3dzdWERqHqUBtDVGMRzQ8fatE0DMArtSw1Hq+az++tpZqY/T zU9LFuLidsvSbhgj5CQlHuHa0rdmmkrH84IBfd49Cz0d1okYIH0UziY+rE8FtqTv9njzf2GXByS 6Krb6WU6I+L0+U5biFTPO1Lh4Deta5KM1HAXS+NNO5u5GVvkGLKcdH57HoLMgfPifDFEWkyUeIP tSrIETslOpi+T6QvBG/TYBG5ff9ljVYjYwfILlvcXATtrdIw6DJ9ldG6PoF3lJapyITlZ3aSloa ocKxnyTEnmCtOyq9eXK5PxWOntBnP3bxTpRb9Q/JFBvuE45wdb6OSNOrXXNi0IOfhZLnJuLkgud 1KB5ittKfTsu6xZLM6kuokYpx20QZgWIWGI8kKPDTBlU3CUXZ5A5xNB+TinGLnssIMGIZIXBI/L aP7mRjWSfHNGtat29FA== X-Authority-Analysis: v=2.4 cv=G+0R0tk5 c=1 sm=1 tr=0 ts=6971e623 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=OE-RsO10cNmVjs9PPLIA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: 1KK3wAeVqdL8Bxl6HAcMVeGhZubWhFQl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-21_04,2026-01-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601220060 On 1/9/2026 9:23 PM, Bjorn Helgaas wrote: > On Fri, Jan 09, 2026 at 12:51:07PM +0530, Krishna Chaitanya Chundru wrote: >> Some platforms keep the PCIe link up across bootloader and kernel >> handoff. In such cases, reinitializing the root complex is unnecessary >> if the DWC glue drivers wants to retain the PCIe link. >> >> Introduce a link_retain flag in struct dw_pcie_rp to indicate that >> the link should be preserved. When this flag is set by DWC glue drivers, >> skip dw_pcie_setup_rc() and only initialize MSI, avoiding redundant >> configuration steps. > It sounds like this adds an assumption that the bootloader > initialization is the same as what dw_pcie_setup_rc() would do. This > assumption also applies to future changes in dw_pcie_setup_rc(). Yes the bootloader is expected to do everything what dw_pcie_setup_r() does. > It looks like you mention an issue like this in [PATCH 4/5]; DBI & ATU > base being different than "HLOS" (whatever that is). This sounds like > a maintenance issue keeping bootloader and kernel driver assumptions > synchronized. As the devicetree changes already pointing to different address from the boatloader, I was trying use this method. As changing device tree properties now might not be good, but no harm in doing so. I can skip this and make device tree changes. > Is there something in dw_pcie_setup_rc() that takes a lot of time or > forces a link retrain? I don't think it might not take much time as it is few register writes, Just doesn't want to do redundant register writes which are costly in general. > You mentioned some clock and GENPD issues in > the cover letter, but I don't see the connection between those and > dw_pcie_setup_rc(). If there is a connection, please include it in > this commit log and include a code comment about why > dw_pcie_setup_rc() is being skipped. The clock and GENPD issues have no direct relation ship with dw_pcie_setup_r(). we are skipping them as they are redundant. I will add a comment in next series on this. - Krishna Chaitanya. >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/controller/dwc/pcie-designware-host.c | 11 ++++++++--- >> drivers/pci/controller/dwc/pcie-designware.h | 1 + >> 2 files changed, 9 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index 372207c33a857b4c98572bb1e9b61fa0080bc871..d050df3f22e9507749a8f2fedd4c24fca43fb410 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -655,9 +655,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) >> if (ret) >> goto err_free_msi; >> >> - ret = dw_pcie_setup_rc(pp); >> - if (ret) >> - goto err_remove_edma; >> + if (!pp->link_retain) { > Use positive logic if possible (test "pp->link_retain" instead of > "!pp->link_retain"). > > I suspect this would be more maintainable if you identified specific > things *inside* dw_pcie_setup_rc() that need to be skipped, and you > added tests there. > >> + ret = dw_pcie_setup_rc(pp); >> + if (ret) >> + goto err_remove_edma; >> + } else { >> + dw_pcie_msi_init(pp); >> + } >> + >> >> if (!dw_pcie_link_up(pci)) { >> ret = dw_pcie_start_link(pci); >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index 31685951a080456b8834aab2bf79a36c78f46639..8acab751b66a06e8322e027ab55dc0ecfdcf634c 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -439,6 +439,7 @@ struct dw_pcie_rp { >> struct pci_config_window *cfg; >> bool ecam_enabled; >> bool native_ecam; >> + bool link_retain; >> }; >> >> struct dw_pcie_ep_ops { >> >> -- >> 2.34.1 >>