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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b98335de177sm622414966b.29.2026.03.24.04.13.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2026 04:13:49 -0700 (PDT) Message-ID: Date: Tue, 24 Mar 2026 12:13:47 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] dt-bindings: clock: qcom,milos-camcc: Document interconnect path To: Mike Tipton Cc: Krzysztof Kozlowski , Luca Weiss , Taniya Das , Georgi Djakov , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20260116-milos-camcc-icc-v1-0-400b7fcd156a@fairphone.com> <20260116-milos-camcc-icc-v1-2-400b7fcd156a@fairphone.com> <20260117-efficient-fractal-sloth-aaf7c2@quoll> <59d9f7ff-4111-4304-a76c-40f4000545f5@oss.qualcomm.com> <9f8619d4-43ac-4bc0-9598-c498d59a27b8@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=VvUuwu2n c=1 sm=1 tr=0 ts=69c271ef cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=WLTbINpYHCHO6pnoh_cA:9 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-GUID: fWVCMjSL5UISl99JEtbSQpG9q_xUcOTU X-Proofpoint-ORIG-GUID: fWVCMjSL5UISl99JEtbSQpG9q_xUcOTU X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI0MDA4OSBTYWx0ZWRfX3fwBou6Nyuwv zqbILoguSwVviixvskufgHOjMz94Kho2YCswbWd4SpesjsP0iDY/8Gs51mMUu0RNdvaUcUB+N7o FF6SrcRUdlgaU4tcqed0FPL0yAqWZ0O2vHMuZ2jFIVLrzax5FLq6MkTwnNgULdTPH0tP89vO+yL mVdBTacM7Uip++poQEh1rSO+CjKOhbGxaEspkYRJYAhCOIlPJCKfR6YAocch/5W8jIut8vvfSZ5 yGIDM1m3MF74Pyvk10oWAi4SUwA7A0j2Kg7fBlqs4Je70q8K+bWrOo68k8vRBqWx1xS/m/9N598 djYfmDm0O0CR34hvWxhDlTpYKPBVMh1K8SkvT0qaYYDzF5qO22xMyD4EBoirE+Yg1ChOsHAmMDM HfwszBFHSq8hXacBWfq8OVH9ZYRc4N1B5XOGt9b14vNxHxLQQfoBfZBMDXn+o6cPLMmwjEYcEjV aybvUvajxmNMc3LYNJw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-24_02,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603240089 On 3/24/26 3:48 AM, Mike Tipton wrote: > On Mon, Jan 19, 2026 at 11:28:07AM +0100, Konrad Dybcio wrote: >> >> >> On 1/19/26 11:20 AM, Konrad Dybcio wrote: >>> On 1/17/26 12:46 PM, Krzysztof Kozlowski wrote: >>>> On Fri, Jan 16, 2026 at 02:17:21PM +0100, Luca Weiss wrote: >>>>> Document an interconnect path for camcc that's required to enable >>>>> the CAMSS_TOP_GDSC power domain. >>>> >>>> I find it confusing. Enabling GDSC power domains is done via power >>>> domains, not via interconnects. Do not represent power domains as >>>> interconnects, it's something completely different. >>> >>> The name of the power domains is CAMSS_TOP_GDSC (seems you misread) >>> >>> For the power domain to successfully turn on, the MNoC needs to be >>> turned on (empirical evidence). The way to do it is to request a >>> nonzero vote on this interconnect path >>> >>> (presumably because the GDSC or its invisible providers require >>> something connected over that bus to carry out their enable sequences). > > The GDSC itself shouldn't depend on MMNOC in order to turn on properly. > It should turn on just fine without it. There *is* a dependency between > CAM_TOP_GDSC and MMNOC, but it's in the opposite direction. > > For MMNOC to turn off properly when all BW votes are removed, the > CAM_TOP_GDSC must already be off. If CAM_TOP_GDSC is still on when MMNOC > starts turning off, then MMNOC will get stuck in its collapse sequence. > MMNOC waits for all HW clients to de-assert their active signals before > it'll allow itself to collapse. Most HW blocks assert this active signal > more dynamically than camera does rather than tying it to GDSC state. > The GDSC asserting active signals to RPMh that prevent NOC collapse is > unique to this particular camera GDSC. > > If MMNOC BW is removed when CAM_TOP_GDSC is still enabled, then it > should reproduce as an icc_set_bw() failure on MMNOC rather than a GDSC > enable failure. The icc_set_bw(0) request would succeed because RPMh > immediately ACKs down requests, but the collapse sequence would get > stuck in the background. Later, when someone calls icc_set_bw() again > with a non-zero BW to enable MMNOC, then that request would fail because > MMNOC is still stuck in the prior collapse sequence. > > Note I haven't explicitly confirmed the Milos behavior, but this has > been the HW dependency for at least several generations of chips now. > I've never seen this GDSC get stuck turning on because MMNOC if off, nor > would I be able to explain offhand why that would happen. But MMNOC > certainly does depend on this GDSC for the reasons stated above. In case that helps, I believe Luca originally observed that keeping the display on, specifically voting on the: &mmss_noc MASTER_MDP <-> &mc_virt SLAVE_EBI1 path made the GDSC power on successfully, lacking that made the problem come back The nodes that are hit on the way are: qnm_mdp (mmss_noc) qns_mem_noc_hf (mmss_noc) qnm_mnoc_hf (gem_noc) qns_llcc (gem_noc) llcc_mc (mc_virt) ebi (mc_virt) That translates into mmss_noc -> MM0, MM1 gem_noc -> SH0, SH1 mc_virt -> ACV, MC0 Notably, all of the foo_camnoc_bar nodes reside on mmss_noc as well. May it be that voting on them ungates a clock that (perhaps recursively) feeds the GDSC? Because the platform is not suspended, the latter two buses are already online, so I'd assume it's one of the MM BCMs that's causing something I can't see any details about its inputs.. In case that's useful, the GCC driver enables the following camera branches as always-on: GCC_CAMERA_AHB_CLK GCC_CAMERA_HF_XO_CLK GCC_CAMERA_SF_XO_CLK Konrad