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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id x4sm674150lfq.246.2021.10.22.01.55.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 22 Oct 2021 01:55:43 -0700 (PDT) Subject: Re: [GIT PULL] riscv: dts: few cleanups for v5.16 To: Palmer Dabbelt , Arnd Bergmann List-Id: Cc: Conor.Dooley@microchip.com, Olof Johansson , arm@kernel.org, soc@kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, krzk@kernel.org, Paul Walmsley , aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org References: From: Krzysztof Kozlowski Message-ID: Date: Fri, 22 Oct 2021 10:55:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 21/10/2021 17:35, Palmer Dabbelt wrote: > On Thu, 21 Oct 2021 08:18:16 PDT (-0700), Arnd Bergmann wrote: >> On Thu, Oct 21, 2021 at 5:06 PM Palmer Dabbelt wrote: >>> On Thu, 21 Oct 2021 06:09:50 PDT (-0700), krzysztof.kozlowski@canonical.com wrote: >>>> >>>> There is only one Microchip patch here (plic/clint). Others are for >>>> SiFive. All the patches are described in the pull reqeust: >>>> https://lore.kernel.org/lkml/20211021090955.115005-1-krzysztof.kozlowski@canonical.com/ >>>> >>>> I had also second set of RISC-V patches for Microchip. These were picked >>>> up by Palmer: >>>> https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/log/?h=for-next >>> >>> Sorry I missed this. If you guys took this through the SOC tree that's >>> fine, otherwise LMK and I'll put it in the RISC-V tree. >> >> I haven't merged it yet, please add it to your tree then. > > OK, it's in. Sorry for missing this, IRC is always a good bet for these > sorts of things as my inbox can get pretty hosed. Great, thanks! Best regards, Krzysztof