From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C86222C028C for ; Mon, 30 Mar 2026 11:34:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774870448; cv=none; b=LmHshG3jOWNFmrfCgD5E95TFnPZtoqeJdWgYPyWMrtyIcD2bKy3/rxbZiz7GyT9BN7G7/gn/07Y0yUxiNVe36KWigHMkC3ZlWYKBIhPnKCL2TiiIwNwNdq+wIzz3DtljU/ajjKPQr9QV709EdkKlUqo5SPJI8kE7DVx4jyF0xPs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774870448; c=relaxed/simple; bh=m+8ovpGCN52xV7rm4mRJHVBz4R/XenTFs+rR+XmL00o=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RkQVFZIABYdQksABCbsr0LSVysm6+uRqi74vnMD8mdBo3M6Hmfz++zSJR0gZXOVjT+gTW0i3oz6icr3jZWzVO7CDWHPYzI2gDP9x7BSLEJgChnc6lSKCIhdIj0vbwgcE5FWbyTNAcM+Sgy3GnbwQy4k04IXhv6cVxp+8hLDaXgI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KCjzBdom; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KCjzBdom" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F13BC2BCB1; Mon, 30 Mar 2026 11:34:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774870448; bh=m+8ovpGCN52xV7rm4mRJHVBz4R/XenTFs+rR+XmL00o=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=KCjzBdom9MM9fRYVKgPUpggHDgj8y8IeCTMytL/EAiP+2jRMH7PWwzSMVJaA6RmrB 6+wyIILtF6t6OveLbllkRaazu1KXEOIoPK7Hs2bG6p8D/u52l7m6gHXhYkqWc1WaAp qQRk9JaSAjhz/LulyymVliwaBRmpaExSkyi1bLf75bs0N9RgFpY2Sw58RI7QT0saz1 i7WFIJxFsX4dkaFtdlr5ahU/6tRg2wlge2/bbkwnEXg69t1VQy+bOWDcu4CY1mewgn pBqoDrLXHHu7pR1ya7/MMtmUsh+fdz5aPOF8RtJucjRvPHCpSZF/I1S/FOf3gHc+aO WQP0u5HwMIwqA== Date: Mon, 30 Mar 2026 12:34:02 +0100 From: Will Deacon To: Carlos Llamas Cc: linux-arm-kernel@lists.infradead.org, Sami Tolvanen , Catalin Marinas , Peter Zijlstra , Josh Poimboeuf , Ard Biesheuvel , Mark Rutland , Kees Cook , Quentin Perret , Steven Rostedt , Will McVicker , Sean Christopherson , kernel-team@android.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7] arm64: implement support for static call trampolines Message-ID: References: <20260313061852.4025964-1-cmllamas@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260313061852.4025964-1-cmllamas@google.com> Hi Carlos, On Fri, Mar 13, 2026 at 06:18:52AM +0000, Carlos Llamas wrote: > From: Ard Biesheuvel > > Implement arm64 support for the 'unoptimized' static call variety, which > routes all calls through a single trampoline that is patched to perform a > tail call to the selected function. > > Since static call targets may be located in modules loaded out of direct > branching range, we need to use a ADRP/ADD pair to load the branch target > into R16 and use a branch-to-register (BR) instruction to perform an > indirect call. Unlike on x86, there is no pressing need on arm64 to avoid > indirect calls at all cost, but hiding it from the compiler as is done > here does have some benefits: > - the literal is located in .rodata, which gives us the same robustness > advantage that code patching does; > - no performance hit on CFI enabled Clang builds that decorate compiler > emitted indirect calls with branch target validity checks. > > Cc: Peter Zijlstra (Intel) > Signed-off-by: Ard Biesheuvel > Signed-off-by: Carlos Llamas > --- > v7: > - Took Ard's v3 patch (as it leaves the code patching logic out) and > rebased it on top of mainline 7.0-rc3. > - Dropped the changes to arch/arm64/lib/insn.c and instead switched to > the (now) existing aarch64_insn_write_literal_u64(). > - Added the RET0 trampoline define which points to the generic stub > __static_call_return0. > - Made the HAVE_STATIC_CALL conditional on CFI as suggested by Ard. > - Added .type and .size sections to the trampoline definition to > support ABI tools. Are you planning to respin this based on Ard's comments? Cheers, Will