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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc7856sm227326415ad.68.2026.01.14.02.29.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 14 Jan 2026 02:29:13 -0800 (PST) Message-ID: Date: Wed, 14 Jan 2026 15:59:07 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/4] arm64: dts: qcom: Introduce Glymur base dtsi To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jyothi Kumar Seerapu , Maulik Shah , Sibi Sankar , Taniya Das , Kamal Wadhwa , Qiang Yu , Manaf Meethalavalappu Pallikunhi , Jishnu Prakash , Abel Vesa References: <20260112-upstream_v3_glymur_introduction-v4-0-8a0366210e02@oss.qualcomm.com> <20260112-upstream_v3_glymur_introduction-v4-3-8a0366210e02@oss.qualcomm.com> Content-Language: en-US From: Pankaj Patil In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: djRWxmbPToUY2E5v0HY4um6gQ_7E2YB_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE0MDA4NSBTYWx0ZWRfX3fG56vza6saN IZtYxwQP6OOAnqG2eKPNl7bjJAl0v8ezxQ4NIBbmnPTlYT1evsJ5Qhp0vUcsKF/TOegVSHvj+Qy TPdbWby8ZFSrKq5kehhW5qXx4FZ4Ew4yWRt8XYbxiL0VdpEZKf2ubPHNbz5dE8W9ySAISVZV2rt 6hZdH65FlliHo9BKIyjrCxPPSQGgzN01aS0GV3GGcKQbVBmVX7fUIgOW5Cc2pE/nQW2a92lesnX BaRUBzjeqBwqrJQLD6xRa9/RmUMc0WbHKdHf5YOfASsdb5FnMLmVPpfwpTDl5iHI102KmIXbGIt HxyKl/VA6gQS/TcTjymtT+CgUBPAWnSbhXjrRS47UE0aCTNYkVqx4WnM7PNMmYEKUrO46Osfd2v E6nwSc3mM4OevzQQveq8SEUAtGDvrdRhlTkPuy+4e9jex+vwin7YX9gYFW2CgcnjCYPcNLt7A8q o2nTRpIyHuk/LqViwpA== X-Authority-Analysis: v=2.4 cv=W+w1lBWk c=1 sm=1 tr=0 ts=69676ffc cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=5tyqGv89VatObklNbhcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: djRWxmbPToUY2E5v0HY4um6gQ_7E2YB_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-14_03,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601140085 On 1/14/2026 9:47 AM, Bjorn Andersson wrote: > On Mon, Jan 12, 2026 at 05:52:36PM +0530, Pankaj Patil wrote: >> Introduce the base device tree support for Glymur – Qualcomm's >> next-generation compute SoC. The new glymur.dtsi describes the core SoC >> components, including: >> >> - CPUs and CPU topology >> - Interrupt controller and TLMM >> - GCC,DISPCC and RPMHCC clock controllers >> - Reserved memory and interconnects >> - APPS and PCIe SMMU and firmware SCM >> - Watchdog, RPMHPD, APPS RSC and SRAM >> - PSCI and PMU nodes >> - QUPv3 serial engines >> - CPU power domains and idle states, plus SCMI/ SRAM pieces for CPU DVFS >> - PDP0 mailbox, IPCC and AOSS >> - Display clock controller >> - SPMI PMIC arbiter with SPMI0/1/2 buses >> - SMP2P nodes >> - TSENS and thermal zones (8 instances, 92 sensors) >> >> Add dtsi files for PMH0101, PMK8850, PMCX0102, SMB2370, PMH0104, >> PMH0110 along with temp-alarm and GPIO nodes needed on Glymur >> >> Enabled PCIe controllers and associated PHY to support boot to >> shell with nvme storage, >> List of PCIe instances enabled: >> >> - PCIe3b >> - PCIe4 >> - PCIe5 >> - PCIe6 >> > > Why didn't you run "make qcom/glymur-crd.dtb CHECK_DTBS=1" before > sending patches to the mailing list?! > > It would taken you 30 seconds to conclude that I can't do anything with > these patches. > > Regards, > Bjorn I've ran the bindings check, dt-bindings specified as dependencies will fix the errors Additionally, I'll drop qup-memory from interconnects for serial and spi in next rev, which cause the bindings errors, this was missed