From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754911AbcHVMQ5 (ORCPT ); Mon, 22 Aug 2016 08:16:57 -0400 Received: from mail-wm0-f48.google.com ([74.125.82.48]:35903 "EHLO mail-wm0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752315AbcHVMQz (ORCPT ); Mon, 22 Aug 2016 08:16:55 -0400 Subject: Re: [RESEND PATCH v2 1/4] pwm: Add support for Meson PWM Controller To: thierry.reding@gmail.com, carlo@caione.org, khilman@baylibre.com References: <1471718083-11516-1-git-send-email-narmstrong@baylibre.com> <1471718083-11516-2-git-send-email-narmstrong@baylibre.com> Cc: linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org From: Neil Armstrong Organization: Baylibre Message-ID: Date: Mon, 22 Aug 2016 14:16:52 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: <1471718083-11516-2-git-send-email-narmstrong@baylibre.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Thierry, On 08/20/2016 08:34 PM, Neil Armstrong wrote: > Add support for the PWM controller found in the Amlogic SoCs. > This driver supports the Meson8b and GXBB SoCs. > > Signed-off-by: Neil Armstrong > --- > drivers/pwm/Kconfig | 9 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-meson.c | 491 ++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 501 insertions(+) > create mode 100644 drivers/pwm/pwm-meson.c > [...] > diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c > new file mode 100644 > index 0000000..9e7ecf5 > --- /dev/null > +++ b/drivers/pwm/pwm-meson.c [...] > + > +static const char * const pwm_parents[] = { > + "xtal", "vid_pll", "fclk_div4", "fclk_div3", NULL > +}; Aww, crap, it's "vid_pll" on meson8b and "hdmi_pll" for gxbb. I'll add it to DT mach data. > +static int meson_pwm_enable(struct pwm_chip *chip, > + struct pwm_device *pwm) > +{ > + struct meson_pwm_chip *pwm_data = to_meson_pwm_chip(chip); > + unsigned int id = pwm->hwpwm; > + unsigned long flags; > + > + spin_lock_irqsave(&pwm_data->lock, flags); > + switch (id) { > + case PWM_A: > + writel(readl(pwm_data->base + REG_MISC_AB) | MISC_A_EN, > + pwm_data->base + REG_MISC_AB); Found an issue here, the HW requires to re-write the clock counts register even if the value is correct. Let's got for a v3 ! > + break; > + > + case PWM_B: > + writel(readl(pwm_data->base + REG_MISC_AB) | MISC_B_EN, > + pwm_data->base + REG_MISC_AB); > + break; > + > + default: > + break; > + } > + spin_unlock_irqrestore(&pwm_data->lock, flags); > + > + return 0; > +} Is it worth rewriting the driver using the apply callback ? I'll wish to have it for 4.9 if possible, do you think it's possible ? Neil