From: Lu Baolu <baolu.lu@linux.intel.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
Auger Eric <eric.auger@redhat.com>
Cc: baolu.lu@linux.intel.com, iommu@lists.linux-foundation.org,
LKML <linux-kernel@vger.kernel.org>,
Joerg Roedel <joro@8bytes.org>,
David Woodhouse <dwmw2@infradead.org>,
"Tian, Kevin" <kevin.tian@intel.com>,
Raj Ashok <ashok.raj@intel.com>, Yi Liu <yi.l.liu@intel.com>
Subject: Re: [PATCH v2 04/10] iommu/vt-d: Match CPU and IOMMU paging mode
Date: Tue, 19 Nov 2019 11:06:10 +0800 [thread overview]
Message-ID: <ad3c3d58-dd1a-4b83-8b30-31e5be9e9c39@linux.intel.com> (raw)
In-Reply-To: <20191118135238.49f5d957@jacob-builder>
Hi Eric and Jacob,
On 11/19/19 5:52 AM, Jacob Pan wrote:
> On Mon, 18 Nov 2019 21:55:03 +0100
> Auger Eric <eric.auger@redhat.com> wrote:
>
>> Hi Jacob,
>>
>> On 11/18/19 8:42 PM, Jacob Pan wrote:
>>> When setting up first level page tables for sharing with CPU, we
>>> need to ensure IOMMU can support no less than the levels supported
>>> by the CPU.
>>> It is not adequate, as in the current code, to set up 5-level paging
>>> in PASID entry First Level Paging Mode(FLPM) solely based on CPU.
>>>
>>> Fixes: 437f35e1cd4c8 ("iommu/vt-d: Add first level page table
>>> interface")
>>> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
>>> Acked-by: Lu Baolu <baolu.lu@linux.intel.com>
>>> ---
>>> drivers/iommu/intel-pasid.c | 12 ++++++++++--
>>> 1 file changed, 10 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/iommu/intel-pasid.c
>>> b/drivers/iommu/intel-pasid.c index 040a445be300..e7cb0b8a7332
>>> 100644 --- a/drivers/iommu/intel-pasid.c
>>> +++ b/drivers/iommu/intel-pasid.c
>>> @@ -499,8 +499,16 @@ int intel_pasid_setup_first_level(struct
>>> intel_iommu *iommu, }
>>>
>>> #ifdef CONFIG_X86
>>> - if (cpu_feature_enabled(X86_FEATURE_LA57))
>>> - pasid_set_flpm(pte, 1);
>>> + /* Both CPU and IOMMU paging mode need to match */
>>> + if (cpu_feature_enabled(X86_FEATURE_LA57)) {
>>> + if (cap_5lp_support(iommu->cap)) {
>>> + pasid_set_flpm(pte, 1);
>>> + } else {
>>> + pr_err("VT-d has no 5-level paging support
>>> for CPU\n");
>>> + pasid_clear_entry(pte);
>>> + return -EINVAL;
>> Can it happen? If I am not wrong intel_pasid_setup_first_level() only
>> seems to be called from intel_svm_bind_mm which now checks the
>> SVM_CAPABLE flag.
>>
> You are right, this check is not needed any more. I will drop the patch.
>> Thanks
I'd suggest to keep this. This helper is not only for svm, although
currently svm is the only caller. For first level pasid setup, let's
set an assumption that hardware should never report mismatching paging
modes, this is helpful especially when running vIOMMU in VM guests.
Best regards,
baolu
next prev parent reply other threads:[~2019-11-19 3:09 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-18 19:42 [PATCH v2 00/10] VT-d Native Shared virtual memory cleanup and fixes Jacob Pan
2019-11-18 19:42 ` [PATCH v2 01/10] iommu/vt-d: Introduce native SVM capable flag Jacob Pan
2019-11-18 20:33 ` Auger Eric
2019-11-18 21:48 ` Jacob Pan
2019-11-19 2:55 ` Lu Baolu
2019-11-19 17:06 ` Jacob Pan
2019-11-18 19:42 ` [PATCH v2 02/10] iommu/vt-d: Fix CPU and IOMMU SVM feature matching checks Jacob Pan
2019-11-18 20:33 ` Auger Eric
2019-11-18 21:47 ` Jacob Pan
2019-11-19 8:02 ` Auger Eric
2019-11-19 17:32 ` Jacob Pan
2019-11-18 19:42 ` [PATCH v2 03/10] iommu/vt-d: Reject SVM bind for failed capability check Jacob Pan
2019-11-18 20:55 ` Auger Eric
2019-11-18 19:42 ` [PATCH v2 04/10] iommu/vt-d: Match CPU and IOMMU paging mode Jacob Pan
2019-11-18 20:55 ` Auger Eric
2019-11-18 21:52 ` Jacob Pan
2019-11-19 3:06 ` Lu Baolu [this message]
2019-11-19 8:04 ` Auger Eric
2019-11-19 17:12 ` Jacob Pan
2019-11-18 19:42 ` [PATCH v2 05/10] iommu/vt-d: Avoid duplicated code for PASID setup Jacob Pan
2019-11-18 20:59 ` Auger Eric
2019-11-18 19:42 ` [PATCH v2 06/10] iommu/vt-d: Fix off-by-one in PASID allocation Jacob Pan
2019-11-18 21:00 ` Auger Eric
2019-11-18 19:42 ` [PATCH v2 07/10] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Jacob Pan
2019-11-18 21:11 ` Auger Eric
2019-11-18 22:16 ` Jacob Pan
2019-11-18 19:42 ` [PATCH v2 08/10] iommu/vt-d: Fix PASID cache flush Jacob Pan
2019-11-18 21:19 ` Auger Eric
2019-11-18 23:38 ` Jacob Pan
2019-11-18 19:42 ` [PATCH v2 09/10] iommu/vt-d: Avoid sending invalid page response Jacob Pan
2019-11-18 21:26 ` Auger Eric
2019-11-18 19:42 ` [PATCH v2 10/10] iommu/vt-d: Misc macro clean up for SVM Jacob Pan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ad3c3d58-dd1a-4b83-8b30-31e5be9e9c39@linux.intel.com \
--to=baolu.lu@linux.intel.com \
--cc=ashok.raj@intel.com \
--cc=dwmw2@infradead.org \
--cc=eric.auger@redhat.com \
--cc=iommu@lists.linux-foundation.org \
--cc=jacob.jun.pan@linux.intel.com \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=yi.l.liu@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome