Re: [PATCH v4 3/5] soc/tegra: pmc: Ensure that clock rates aren't too high

[Dmitry Osipenko <digetx@gmail.com>]

25.03.2021 18:02, Dmitry Osipenko пишет:
> 25.03.2021 17:39, Thierry Reding пишет:
>> On Tue, Mar 02, 2021 at 03:25:00PM +0300, Dmitry Osipenko wrote:
>>> Switch all clocks of a power domain to a safe rate which is suitable
>>> for all possible voltages in order to ensure that hardware constraints
>>> aren't violated when power domain state toggles.
>>>
>>> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
>>> Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
>>> Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
>>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>>> ---
>>>  drivers/soc/tegra/pmc.c | 92 ++++++++++++++++++++++++++++++++++++++++-
>>>  1 file changed, 90 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>> index f970b615ee27..a87645fac735 100644
>>> --- a/drivers/soc/tegra/pmc.c
>>> +++ b/drivers/soc/tegra/pmc.c
>>> @@ -237,6 +237,7 @@ struct tegra_powergate {
>>>  	unsigned int id;
>>>  	struct clk **clks;
>>>  	unsigned int num_clks;
>>> +	unsigned long *clk_rates;
>>>  	struct reset_control *reset;
>>>  };
>>>  
>>> @@ -641,6 +642,57 @@ static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
>>>  	return 0;
>>>  }
>>>  
>>> +static int tegra_powergate_prepare_clocks(struct tegra_powergate *pg)
>>> +{
>>> +	unsigned long safe_rate = 100 * 1000 * 1000;
>>
>> This seems a bit arbitrary. Where did you come up with that value?
>>
>> I'm going to apply this to see how it fares in our testing.
> 
> This value is chosen based on the OPP table voltages and frequencies.
> 
> Maybe you could add this clarifying comment to the code(?):
> 
> "There is no hardware unit on any of Tegra SoCs which requires higher
> voltages for the rates above 100MHz."

I meant below, of course :)