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Fri, 23 Oct 2026 10:10:59 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-ThreadId: AmcrnnMArev7 Date: Fri, 23 Oct 2026 16:10:23 +0200 From: "Arnd Bergmann" To: "Fuad Tabba" , "Marc Zyngier" Cc: "Oliver Upton" , kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, "Joey Gouly" , "Suzuki K Poulose" , "Zenghui Yu" , "Steffen Eiden" , "Catalin Marinas" , "Will Deacon" , "Mark Rutland" , "Yicong Yang" , "Zhou Wang" , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Message-Id: In-Reply-To: References: <20261023070110.1833446-1-fuad.tabba@linux.dev> <20261023070110.1833446-2-fuad.tabba@linux.dev> <86fqxwzul7.wl-maz@kernel.org> <86ecdgzp6m.wl-maz@kernel.org> Subject: Re: [PATCH 1/2] KVM: arm64: Hide FEAT_LS64_ACCDATA from guests Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, Oct 23, 2026, at 12:37, Fuad Tabba wrote: > On Fri, 23 Oct 2026 11:28:17 +0100, Marc Zyngier wrote: > [...] >> No, I want this fixed by enabling ACCDATA support by default, which is >> what we have *already* promised to userspace, and see the fireworks. >> You can add an arm64.nols64 kernel option if you want, which is >> consistent with what we do for CNTPOFF, NV3, and other extensions that >> depend on FW enabling them. > > Will do. v2 will have your patches 3 and 4 from [1] rebased, EnAS0 set > when the guest has LS64_ACCDATA, and an arm64.nols64 option. That sounds good. For reference, I have prototyped support for LS64_ACCDATA in Linux drivers based on the corresponding x86 code. The code is not yet tested on hardware, but it may help understand how this may be used in the future. Arnd ---- From: Arnd Bergmann Subject: [PATCH] arm64: dynamically enable st64bv0 for SVA I/O devices that understand the st64bv0 instruction for doing shared virtual access from userspace need to set the pasid value in the accdata_el1 register, but in general we want this to be disabled unless a driver actually hands an MMIO area to userspace that accepts these commands and installs a pasid using iommu_sva_bind_device(). Rather than trying to find all threads that use an mm_struct by the time the pasid created, iommu_sva_bind_device() only stores the pasid in 'struct iommu_mm_data' and sets up the iommu domain in the device. The first attempt to use SVA from userspace traps into do_el0_other(), which checks that this is indeed valid and then sets the configured pasid before enabling SCTLR_EL1_EnAS0. This is pretty much a lifted from the x86 try_fixup_enqcmd_gp() function. Signed-off-by: Arnd Bergmann diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h index a2da3cb21c24..7c61b50718d6 100644 --- a/arch/arm64/include/asm/exception.h +++ b/arch/arm64/include/asm/exception.h @@ -81,6 +81,7 @@ void do_el0_sys(unsigned long esr, struct pt_regs *regs); void do_sp_pc_abort(unsigned long addr, unsigned long esr, struct pt_regs *regs); void bad_el0_sync(struct pt_regs *regs, int reason, unsigned long esr); void do_el0_cp15(unsigned long esr, struct pt_regs *regs); +void do_el0_other(struct pt_regs *regs, unsigned long esr); int do_compat_alignment_fixup(unsigned long addr, struct pt_regs *regs); void do_el0_svc(struct pt_regs *regs); void do_el0_svc_compat(struct pt_regs *regs); diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 803b68758152..55965d752ad5 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -247,6 +248,20 @@ static inline void __switch_mm(struct mm_struct *next) check_and_switch_context(next); } +/* switch to PASID if new task has enabled st64bv0 */ +static inline void switch_iommu_mm(struct mm_struct *mm, struct task_struct *tsk) +{ + u32 pasid; + + if (!IS_ENABLED(CONFIG_IOMMU_SVA) || + !(tsk->thread.sctlr_user & SCTLR_EL1_EnAS0)) + return; + + pasid = mm_get_enqcmd_pasid(mm); + if (pasid != IOMMU_PASID_INVALID) + write_sysreg(pasid, accdata_el1); +} + static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) @@ -254,6 +269,8 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, if (prev != next) __switch_mm(next); + switch_iommu_mm(next, tsk); /* FIXME: is there a better place to do this? */ + /* * Update the saved TTBR0_EL1 of the scheduled-in task as the previous * value may have not been initialised yet (activate_mm caller) or the diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c index 11d3f888fcd8..abeffb7f1fb2 100644 --- a/arch/arm64/kernel/entry-common.c +++ b/arch/arm64/kernel/entry-common.c @@ -806,6 +806,14 @@ static void noinstr el0_fpac(struct pt_regs *regs, unsigned long esr) arm64_exit_to_user_mode(regs); } +static void noinstr el0_other(struct pt_regs *regs, unsigned long esr) +{ + arm64_enter_from_user_mode(regs); + local_daif_restore(DAIF_PROCCTX); + do_el0_other(regs, esr); + arm64_exit_to_user_mode(regs); +} + asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs) { unsigned long esr = read_sysreg(esr_el1); @@ -869,6 +877,9 @@ asmlinkage void noinstr el0t_64_sync_handler(struct pt_regs *regs) case ESR_ELx_EC_FPAC: el0_fpac(regs, esr); break; + case ESR_ELx_EC_OTHER: + el0_other(regs, esr); + break; default: el0_inv(regs, esr); } diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index d6391ab20db3..ce968cce11e7 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -543,6 +544,55 @@ void do_el1_mops(struct pt_regs *regs, unsigned long esr) kernel_fastforward_single_step(regs); } +/* + * PASID/ACCDATA is shared by the entire mm, while sctlr_el1 + * is maintained per thread. Keep things simple and enable + * ACCDATA dynamically on first access if available. + * + * After exiting back to userspace, the st64bv0 instruction + * should no longer trap. + */ +static bool try_enable_st64bv0(struct pt_regs *regs, unsigned long esr) +{ + u32 pasid; + u64 isar1; + u64 sctlr; + + pasid = mm_get_enqcmd_pasid(current->mm); + if (pasid == IOMMU_PASID_INVALID) + return false; + + isar1 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR1_EL1); + if (!(isar1 & ID_AA64ISAR1_EL1_LS64_LS64_ACCDATA)) + return false; + + sysreg_clear_set(accdata_el1, ACCDATA_EL1_ACCDATA, pasid); + sctlr = current->thread.sctlr_user; + sctlr |= SCTLR_EL1_EnAS0; + current->thread.sctlr_user = sctlr; + update_sctlr_el1(sctlr); + + return true; +} + +void do_el0_other(struct pt_regs *regs, unsigned long esr) +{ + switch (ESR_ELx_ISS(esr)) { + case ESR_ELx_ISS_OTHER_ST64BV0: + if (try_enable_st64bv0(regs, esr)) + return; + break; + + case ESR_ELx_ISS_OTHER_ST64BV: + case ESR_ELx_ISS_OTHER_LDST64B: + default: + break; + } + + /* Treat all other "other" trapping instructions as illegal opcode */ + force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); +} + #define __user_cache_maint(insn, address, res) \ if (address >= TASK_SIZE_MAX) { \ res = -EFAULT; \ @@ -842,6 +892,7 @@ static const char *esr_class_str[] = { [ESR_ELx_EC_FP_ASIMD] = "ASIMD", [ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", [ESR_ELx_EC_PAC] = "PAC", + [ESR_ELx_EC_OTHER] = "OTHER", [ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", [ESR_ELx_EC_BTI] = "BTI", [ESR_ELx_EC_ILL] = "PSTATE.IL", diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index b15a59b9e95d..e358d9ad229b 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3656,6 +3656,11 @@ Sysreg TPIDR_EL1 3 0 13 0 4 Field 63:0 ThreadID EndSysreg +Sysreg ACCDATA_EL1 3 0 13 0 5 +Res0 63:32 +Field 31:0 ACCDATA +EndSysreg + Sysreg RCWMASK_EL1 3 0 13 0 6 Field 63:0 RCWMASK EndSysreg