From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01B8326E719 for ; Wed, 10 Dec 2025 14:08:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765375689; cv=none; b=sCbc+mn8kxh+gYe1sYeHsHWz0DUQv3C3m3z//okXB60Ofz0juUOFUyDsRbdY1L/Igf7N77Rc9/z/7wGqs3+cgTwbzQvy2kuM712aqy5AiBJNeWhsDYmhxiPEaP0nQhdNr+/6XwBWeQohOpbvbx4jUX41s6475em7HHUlFurysUg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765375689; c=relaxed/simple; bh=UxEMbnlMWCPLbfZaf0qqk1BfB3mLN1C2so/Ble8ymU8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NSx1z9EGWVKtMfMrpLRqhRx/igi+/Hp+cb2s5+jDdaRu305sS6sTfCH4nxnxPYSg42pMJfdPF8JVoGRmVeO54UfupMAbvpP+EKuDHkf+cE2Q3/XO02n+V8Nynwm3iyvsUGpAXlexpEpjviFbR0FCvfs+7k4kdoHxdAIstLUwR8g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ursulin.net; spf=pass smtp.mailfrom=ursulin.net; dkim=pass (2048-bit key) header.d=ursulin.net header.i=@ursulin.net header.b=fP5PhI7N; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ursulin.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ursulin.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ursulin.net header.i=@ursulin.net header.b="fP5PhI7N" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-b770f4accc0so976680466b.1 for ; Wed, 10 Dec 2025 06:08:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin.net; s=google; t=1765375686; x=1765980486; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=6qbLwM8j/Dp2wxJ0nCOaKXGlVqK4PTIUeJRBwEf/i0c=; b=fP5PhI7NwrI+6AczDv+nTTpVqZO0DDP9LQmgYtnK3x50YBoay6MxHRWOS2TOBdN5UV 2Rq97dVLZDYkMYSUfDson2hGt5H18VlWheWWmRkrh00Co7zcWCvSJzKK62JjkWSlbuUs lyXUewG1L92XsfCD/4WIsHNvWe432qHktGe0FFH98zOE2IwGm4qR2WPRx9GLFN26LTRW INDPGg2RK6vr39dxH24t8RVTtyMbqDs8Zj0hLFONhyPnXA1x+vOP3MWEyiX6oy1/UPXv d6A0LQKNvo5I+CVAfdNi0PSMeUUB4jxaLBWVdd96EFqIju0MzMBG6S1LOl1V2UVznGD2 dMqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765375686; x=1765980486; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6qbLwM8j/Dp2wxJ0nCOaKXGlVqK4PTIUeJRBwEf/i0c=; b=rUe/pGl/XPJX+F422aHPUNYFXlPlxExbAIG9uVQNy2g3g0+fwbWaWNJ0BZkLjJ/hAA UUncVlfKiNzFQvpiY9nl+ChVx90BgIudR1bsRYQ7F57dY44HortVBe8bD7hCQBRybdk3 CQfPukNadkPGEN9fLgDs/8ctrn2Vjnkw3hXVrbwIZdEaZUTZtbpURtsdaaa8CH/VBkvd u2OgKkZ2CIFg7B/H9Q6eRdUBp9dTL+wwz6gTHC/AgxBFTfalAROJhJ1iPMk+NiR2C8H7 JbCYgb/fQrG5YbrazsvyE847fw2TcVsZrCNS2/HRA8PK6O59pgWIqoCTJFPOhSgVwr0q l6OA== X-Gm-Message-State: AOJu0YyG3onRAAzokMI7ecBcsp63yxvJFyg2RFt43B28F6zvoh1QmczC ISq8toCaMswuq6qe1s8QjspJO/qdQEtdueKB6miZk7VqgfUFd7xmEhufSU9cHSWvyZg= X-Gm-Gg: ASbGncu8QDmQQWfuvZqG6MT7SdQ8XIO/SxGU63q8QNMgBZjq78g+AzFhubiRa3NZAF9 OQ0t0DGce2V4EoAeDlyJb5U/5CHU7ekh2dMxh4K2ejPErBF1IYqZz8x5caCHGGRW45ToJsDw72I amidN9SeqMR8+ykWVLnMVxDnGW75oE5ugZYI0YXXOXxQxj6s93J2CdWTtrFSf8UxkU49s99Qumk duGMxLxQa5anuQyIRC7qO8dewBOiWaht65xTMBvXwr4KG8jBqEp+5S0sujz3a/qqaFRU2HV97O3 sVz+OYxMNrHb2jPoUZSOYG15Ijx8yIhzvN+iAwN0pCff8wMdN3Pb9a4/mAVTmjdt/79Rzhp3mio 73XYC4Vmrvlol4KUyiQmrxYe6vdn+P41I1ZUT+3UizD9Kn2LRTdX/mTvjw1Gd6F+jcVVgEiZLe8 MXvwGMyVCIOlVBJbraoBl+EHYFofeW X-Google-Smtp-Source: AGHT+IHWTYS/KWvzDjVFuOADEcyGTh4hEuGU6HfoOi1vw95aIAPW/e3jMvFNIkGOnIlpnosFn6AeVw== X-Received: by 2002:a17:907:86a6:b0:b73:59b0:34d6 with SMTP id a640c23a62f3a-b7ce846eba8mr268666666b.33.1765375685778; Wed, 10 Dec 2025 06:08:05 -0800 (PST) Received: from [192.168.1.83] ([86.33.28.86]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf71fsm18473274a12.14.2025.12.10.06.08.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Dec 2025 06:08:04 -0800 (PST) Message-ID: Date: Wed, 10 Dec 2025 15:08:02 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/i915: Fix BO alloc flags To: =?UTF-8?Q?Lo=C3=AFc_Molinari?= , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Boris Brezillon , =?UTF-8?Q?Miko=C5=82aj_Wasiak?= , Andi Shyti , Christopher Healy Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, kernel@collabora.com, Chaitanya Kumar Borah References: <20251210110952.691446-1-loic.molinari@collabora.com> Content-Language: en-GB From: Tvrtko Ursulin In-Reply-To: <20251210110952.691446-1-loic.molinari@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 10/12/2025 12:09, Loïc Molinari wrote: > I915_BO_ALLOC_NOTHP must be added to the I915_BO_ALLOC_FLAGS mask in > order to pass GEM_BUG_ON() valid flags checks. > > Reported-by: Chaitanya Kumar Borah > Closes: https://lore.kernel.org/intel-gfx/d73adfa8-d61b-46b3-9385-dde53d8db8ad@intel.com/ > Fixes: a8a9a590221c ("drm/i915: Use huge tmpfs mountpoint helpers") > Suggested-by: Tvrtko Ursulin > Signed-off-by: Loïc Molinari > --- > drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > index f94409e8ec4c..35d4c7d0c579 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h > @@ -363,6 +363,7 @@ struct drm_i915_gem_object { > I915_BO_ALLOC_PM_EARLY | \ > I915_BO_ALLOC_GPU_ONLY | \ > I915_BO_ALLOC_CCS_AUX | \ > + I915_BO_ALLOC_NOTHP | \ > I915_BO_PREALLOC) > #define I915_BO_READONLY BIT(10) > #define I915_TILING_QUIRK_BIT 11 /* unknown swizzling; do not release! */ Acked-by: Tvrtko Ursulin It is passing BAT so I think it is fine to go ahead and merge it. Of course via the same branch where the breakage is ie. drm-misc. Regards, Tvrtko