From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BA25A244661 for ; Wed, 8 Apr 2026 09:08:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775639298; cv=none; b=h/x5IG2hZqk+jFJRUs2FP8g7m4NOugHmDFrlfFCpjWpAw7jaadfiGqkLmT/1Awqb4CVrHyFpgKRrZvkQ+O7X7UWlA9kfyd5qc8+s0nHXELWStRDVOQxAEChT+539loqQ7n2llrX2O++Gac7uut4NS9TQdUgGZJS9BX4orLQJVBk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775639298; c=relaxed/simple; bh=eYsNaqDHlg8/2JcSmkyzzh4rtE74LSwT/A1zsvFOkBs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=uVIeYKZ6LaWkb+QSWUUcwR4K6rixKkanml7a6LakkS0VqM+AInEcWmmJeDQebTtO5VZINX0aEEv4JrZFv+GwEJIg58bB8rAFJSImVE/4fueTpxMVkkr6evRs0cWZTy35dvd/jRIEquUxo9Zex3o+av6+gCL2V3mpkZucMi2oXeI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vZzqAejP; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vZzqAejP" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6F84B267F; Wed, 8 Apr 2026 02:08:10 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8C8C93FDE2; Wed, 8 Apr 2026 02:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1775639296; bh=eYsNaqDHlg8/2JcSmkyzzh4rtE74LSwT/A1zsvFOkBs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=vZzqAejPO+Rpcr5AYtK/8W9nRqL0AZ+mAcrftfV16DTCS8r0mMEoZR3tx4N5VuLB6 kVT7njKLSrJpqVAPfUOul1TrMbTINuotgBbAxHvIbgYA5/sPSceSIXoQdDWdinE9OF /6Pg+FlOtf0cKMk9Rmc9/ueJXjVUVx8wQ0hBOYf8= Date: Wed, 8 Apr 2026 10:08:12 +0100 From: Mark Rutland To: Jinjie Ruan Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , ada.coupriediaz@arm.com, linux-kernel@vger.kernel.org, luto@kernel.org, peterz@infradead.org, tglx@kernel.org, vladimir.murzin@arm.com Subject: Re: [PATCH 10/10] arm64: Check DAIF (and PMR) at task-switch time Message-ID: References: <20260407131650.3813777-1-mark.rutland@arm.com> <20260407131650.3813777-11-mark.rutland@arm.com> <26642def-7676-e081-98f3-9ab883048375@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <26642def-7676-e081-98f3-9ab883048375@huawei.com> On Wed, Apr 08, 2026 at 10:17:56AM +0800, Jinjie Ruan wrote: > On 2026/4/7 21:16, Mark Rutland wrote: > > +static inline void debug_switch_state(void) > > +{ > > + if (system_uses_irq_prio_masking()) { > > + unsigned long daif_expected = 0; > > + unsigned long daif_actual = read_sysreg(daif); > > + unsigned long pmr_expected = GIC_PRIO_IRQOFF; > > + unsigned long pmr_actual = read_sysreg_s(SYS_ICC_PMR_EL1); > > + > > + WARN_ONCE(daif_actual != daif_expected || > > + pmr_actual != pmr_expected, > > + "Unexpected DAIF + PMR: 0x%lx + 0x%lx (expected 0x%lx + 0x%lx)\n", > > + daif_actual, pmr_actual, > > + daif_expected, pmr_expected); > > + } else { > > + unsigned long daif_expected = DAIF_PROCCTX_NOIRQ; > > + unsigned long daif_actual = read_sysreg(daif); > > + > > + WARN_ONCE(daif_actual != daif_expected, > > + "Unexpected DAIF value: 0x%lx (expected 0x%lx)\n", > > + daif_actual, daif_expected); > > + } > > This logic seems consistent with arm64's local_irq_disable() > implementation. Do we need to wrap these debug checks in a config option > (e.g., CONFIG_ARM64_DEBUG_PRIORITY_MASKING) to avoid unnecessary overhead? Possibly. I'd expected this was infrequent enough that there wouldn't be a noticeable overhead, but admittedly I don't have numbers. Given Thomas seems happy to queue the preparatory bits, (hopefully) we can queue the rest of this as-is, and I reckon it's probably best to drop this patch for now and follow up with a better version later. There are some other bits of state I'd like to check here (e.g. PAN), and I think this requires a bit more work. Thanks for looking at this! Mark. > > > __schedule() > -> local_irq_disable() > -> arch_local_irq_disable() > > 52 static __always_inline void __daif_local_irq_disable(void) > 53 { > 54 barrier(); > 55 asm volatile("msr daifset, #3"); > 56 barrier(); > 57 } > 58 > 59 static __always_inline void __pmr_local_irq_disable(void) > 60 { > 61 if (IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING)) { > 62 u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1); > 63 WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != > GIC_PRIO_IRQOFF); > 64 } > 65 > 66 barrier(); > 67 write_sysreg_s(GIC_PRIO_IRQOFF, SYS_ICC_PMR_EL1); > 68 barrier(); > 69 } > 70 > 71 static inline void arch_local_irq_disable(void) > 72 { > 73 if (system_uses_irq_prio_masking()) { > 74 __pmr_local_irq_disable(); > 75 } else { > 76 __daif_local_irq_disable(); > 77 } > 78 } > > > > +} > > + > > /* > > * Thread switching. > > */ > > @@ -708,6 +731,8 @@ struct task_struct *__switch_to(struct task_struct *prev, > > { > > struct task_struct *last; > > > > + debug_switch_state(); > > + > > fpsimd_thread_switch(next); > > tls_thread_switch(next); > > hw_breakpoint_thread_switch(next);