From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752640AbdLKSuh (ORCPT ); Mon, 11 Dec 2017 13:50:37 -0500 Received: from mail-lf0-f68.google.com ([209.85.215.68]:45212 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752126AbdLKSuf (ORCPT ); Mon, 11 Dec 2017 13:50:35 -0500 X-Google-Smtp-Source: ACJfBot4rdhSqWXDnXBY/1MNUzE6B4c8lKDW0fODauYFFKtWZpQ21xOBHs3bSQw2HWOugoBXjBAGJQ== From: Dmitry Osipenko To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X Date: Mon, 11 Dec 2017 21:50:09 +0300 Message-Id: X-Mailer: git-send-email 2.15.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cpufreq driver uses 216 MHz as the lowest CPU clock frequency, but clock driver doesn't provide that rate, so the requested clock is rounded up to 312 MHz. Let's add entry for 216 MHz to match with cpufreq. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index cbd5a2e5c569..e33d7548a4e9 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -269,6 +269,11 @@ static struct tegra_clk_pll_freq_table pll_x_freq_table[] = { { 13000000, 312000000, 312, 13, 1, 12 }, { 19200000, 312000000, 260, 16, 1, 8 }, { 26000000, 312000000, 312, 26, 1, 12 }, + /* 216 MHz */ + { 12000000, 216000000, 216, 12, 1, 12 }, + { 13000000, 216000000, 216, 13, 1, 12 }, + { 19200000, 216000000, 180, 16, 1, 8 }, + { 26000000, 216000000, 216, 26, 1, 12 }, { 0, 0, 0, 0, 0, 0 }, }; -- 2.15.1