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Thu, 04 Dec 2025 02:36:17 -0800 (PST) Received: from hu-pkondeti-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34912897600sm2451156a91.0.2025.12.04.02.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 02:36:17 -0800 (PST) Date: Thu, 4 Dec 2025 16:06:12 +0530 From: Pavan Kondeti To: Marc Zyngier Cc: Pavan Kondeti , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, rsalveti@oss.qualcomm.com Subject: Re: Alternative to arm64.nopauth cmdline for disabling Pointer Authentication Message-ID: References: <3fcf6614-ee83-4a06-9024-83573b2e642e@quicinc.com> <86ecpappzi.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86ecpappzi.wl-maz@kernel.org> X-Proofpoint-GUID: FRZm3NunwOlnEb4noLzF6Q56UOnSYQ1f X-Proofpoint-ORIG-GUID: FRZm3NunwOlnEb4noLzF6Q56UOnSYQ1f X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA0MDA4NiBTYWx0ZWRfX2h8cXNN/uEXk kb4ViK9GiDD36ueWRGY2ceqLqQkhPwonKnE9lVG6optTrVrV9I0uJY4sasyRQiWV2MCamDCSrfg v9FsKFknFIAVeknY0OIxhMLQ+O64nlxI12O2AKIO/J2fzYc0DL6GsjyvxqRDWtr7isTEXtWM0ex XAxasksENVa2q2HXgjDD958cD5wlkBzFzfrwNLnBIzZ7zJeABtgLd1j9jEEIZnE6Qn42Q1tlp0m n/jPU5mm57+xAd/lqj1MW+t0yKLB3aFY7Ty8LlcOFmo2Eo3ojcDjU1zJJSeWbi9zeUqitEGyRpm UODkXhjMhg30AhOXhBQPNWCRKqVGVx/O1dObKstn46vHoGr8MkDEkfWkphpY4bp3R1b+Nb3LvN2 qJ+EmQWZHI+b70mHQcwdqWA/Vg1wKg== X-Authority-Analysis: v=2.4 cv=Scz6t/Ru c=1 sm=1 tr=0 ts=69316423 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=kj9zAlcOel0A:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=hN0DXoGWr_mGFEF8OEoA:9 a=CjuIK1q_8ugA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-04_02,2025-12-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 impostorscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512040086 Hi Marc, On Thu, Dec 04, 2025 at 09:15:29AM +0000, Marc Zyngier wrote: > On Thu, 04 Dec 2025 04:07:15 +0000, > Pavan Kondeti wrote: > > > > Hi > > > > The pointer authentication feature (PAuth) is only supported on > > 0-3 CPUs but it is not supported on 4-7 CPUS on QCS8300. > > On what grounds? Hardware incompatibility? I seriously doubt it, since > nobody glues pre-8.3 CPUs to anything more modern. Or, as I expect it, > a firmware implemented with little understanding of what is required? I don't know the answer to this question. I will talk to folks who may know answer to this question and get back. Can you please elaborate on the firmware part you are talking here? I see that Linux runs at EL2 and AA64ISAR1 register values on CPU#0 (A78) indicates that PAuth is supported but not for CPU#4 (A55). I am told, there are no other controls outside EL2 (trap) to manipulate this feature. So, I am assuming that this is indeed reflecting the HW. > > > The ARM64 cpufeature discovery code expects late CPUs to have > > this feature if boot CPU feature has it since PAuth is enabled > > early. When a conflict like this is detected, the late CPUs are > > not allowed to boot. It is expected that system will continue > > to be functional with CPUs with Pauth feature supported and enabled. > > This is not a desired behavior in production. > > What is even less desirable is to produce this sort of contraption. > > > We started seeing this problem when Linux is booted in EL2. When Linux > > is running under Gunyah (Type-1 hypervisor), Pointer Authentication > > feature is hidden from EL1 via HCR_EL2.TID3. > > > > arm64.nopauth can be passed on kernel cmdline to disable the feature > > in kernel so that all all CPUs can boot on QCS8300. I am told > > maintaining a custom kernel commandline per SoC in a Generic OS > > distribution is not recommended and asked to discuss the problem with > > the comunity [1] > > Well, you get to own the problem you have created for yourself. You > build hardware/firmware that cannot run generic SW, and yet you want > generic SW to run seamlessly on it. Spot the issue? > > > This patch [2] from Catalin adds a devicetree property under memory {} > > to disable MTE. I believe this work predates the id-reg override > > mechanism. However, this made me think if workarounds like this can be > > detected via devicetree, for example a property under cpu { } node. > > Not only it predates it, but it also doesn't work in general. For a > start, it is DT specific. How are you going to make that work for > ACPI? I know you don't care, but I do. Point taken. I understand that this does not fall under errata but is there a possiblity to introduce an Errata targeting CPU#0 MIDR and disabling the Pointer authentication? I understand that if there is another Qualcomm SoC that exists with all CPUs supporting pointer authentication with same MIDR, we may be disabling the feature but this is something I can check internally. > > > Given that what we put in `chosen { bootargs="" }` kernel under > > respective SoC devicetree can be overridden by bootloader, should we > > have a **sticky** cmdline to specify critical workarounds like this? > > This would be more generic than introducing any new parameters. > > You already have a way to have a sticky command-line, by building it > into the kernel. Yes, I understand that this isn't what you want, but: > > (1) a user should be allowed to pass the kernel command-line *they* > want, not what someone has decided for them Agreed. This is what made me to ask the question. Should kernel have a sticky command line which may have critical workarounds like this? > > (2) the generic mechanism exists, doesn't rely on additional firmware > specifications, and is used for a whole lot of other QC platforms > suffering from the same issue of broken firmware. What are you > going to do for these? The generic mechanism, you mean bootloader passing the kernel cmdline with `arm64.nopauth`? or something else. > > (3) what if you, by miracle, happened to *fix* the firmware? As I have asked above, the firmware part is not clear. Thanks Marc for your time and guidance. Thanks, Pavan