From: Michal Simek <michal.simek@amd.com>
To: <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>,
<michal.simek@xilinx.com>, <git@xilinx.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
"Conor Dooley" <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh@kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>
Subject: [PATCH] dt-bindings: riscv: cpus: Add AMD MicroBlaze V 64bit compatible
Date: Tue, 22 Jul 2025 09:25:40 +0200 [thread overview]
Message-ID: <adf316c097ae416eb8565f2f1d67a98c413a71d2.1753169138.git.michal.simek@amd.com> (raw)
32bit version has been added by commit 4a6b93f56296 ("dt-bindings: riscv:
cpus: Add AMD MicroBlaze V compatible") but 64bit version also exists and
should be covered by binding too.
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 2c72f148a74b..1a0cf0702a45 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -45,6 +45,7 @@ properties:
- items:
- enum:
- amd,mbv32
+ - amd,mbv64
- andestech,ax45mp
- canaan,k210
- sifive,bullet0
--
2.43.0
next reply other threads:[~2025-07-22 7:25 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-22 7:25 Michal Simek [this message]
2025-07-22 15:18 ` Conor Dooley
2025-07-22 15:37 ` Michal Simek
2025-07-22 20:46 ` Conor Dooley
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