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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36ca39972d4sm17734198eec.26.2026.11.04.15.00.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Nov 2026 15:00:52 -0800 (PST) Message-ID: Date: Wed, 4 Nov 2026 15:00:51 -0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] arm64: dts: qcom: lemans: add CSI2 D-PHY common-phy providers To: Nihal Kumar Gupta , Bryan O'Donoghue Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , gjorgji.rosikopulos@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, jigarkumar.zala@oss.qualcomm.com, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Vikram Sharma , Suresh Vankadara References: <20261103221026.3662383-1-anusha.nandi@oss.qualcomm.com> <20261103221026.3662383-2-anusha.nandi@oss.qualcomm.com> <72223121-cb42-422f-8ce5-4cf9f41c5aec@oss.qualcomm.com> Content-Language: en-US From: Anusha Arun Nandi In-Reply-To: <72223121-cb42-422f-8ce5-4cf9f41c5aec@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA0MDA5MCBTYWx0ZWRfXyL0oRkm9463G DnWVG1VVNz4Q3jk66REO56VuNmdaFhfHul506C3+rr0qyiuJosrCnxuRhZyiiVmFgwETrcoodZD kzpgc2ff5H/4JXI0l79kKFRHmjoOPWw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA0MDA5MCBTYWx0ZWRfX43H9kjB0/2So D2DXD1sefezYJb+1KeAliAGf2UOGmFl8+CC2RxD89iABPQm0REXjZ8qAsEuWPFjE4Its5XjYrie iRfLHqBe2G8OzO1c2c4s76Ts20ZMtXZK4xUWgKiG+Rlwh2w9ud0BhMCPzzWjKfnQezT8yO9K+5W B24GnDRjzYaUGx0KyUcjPFNuOdJqZpEIwVKMDQWdASdGo/lr+LH5cG38eCfjlUS+suZUxQvTqbD b+w/4NprP6quNzEmeCGErZlKATiX5PKT/vfHGLxIUcSS+Ds3xnAIWumtrYno2WeYTeuS6FTJds5 0w6griZug331HQ+iQP2KrI0aziGbZVfT6egWR8F/AlOav+dNUTZxp/c1HRqqrn16qQ/tT8kfmPw fXlLFS82Ic/vOlz/ndrDKt+SqjkepwMqd1dOlUiGTu877MjPx3Tdwp7i7J+fgvW2XFvB9adjta7 zk/OwdOCwFS43PKulcw== X-Proofpoint-ORIG-GUID: iCvxag__N9yd2LX1f9_okJ-2vlQ8mDYF X-Authority-Analysis: v=2.4 cv=D4XSufRj c=1 sm=1 tr=0 ts=6aebb926 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=YzLprhzs-1J5OMutLZIA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: iCvxag__N9yd2LX1f9_okJ-2vlQ8mDYF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-04_05,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 clxscore=1015 suspectscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611040090 Hi Nihal, will drop a new patchset. Thank you Anusha On 11/3/2026 8:53 PM, Nihal Kumar Gupta wrote: > > > On 04-11-2026 03:40, Anusha Arun Nandi wrote: >> Expose the four SA8775p CSIPHYs as standalone qcom,sa8775p-csi2-phy >> generic-PHY provider nodes (csiphy0..3) at their existing register >> addresses, each with its own OF graph (port@0 sensor-facing, port@1 >> CAMSS-facing) so camss_detect_legacy_phy() picks the non-legacy path >> once a board wires a sensor through one of them. The camss node's own >> reg-names/clocks/interrupts for the CSIPHYs are unchanged, so boards >> that don't use a provider still get the legacy binding. >> >> The provider nodes are disabled by default; a board or camera overlay >> enables the one(s) it uses. >> >> Reviewed-by: Jigarkumar Zala >> Signed-off-by: Anusha Arun Nandi >> --- >> arch/arm64/boot/dts/qcom/lemans.dtsi | 140 +++++++++++++++++++++++++++ >> 1 file changed, 140 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi >> index 1fdb72fa5518..2a30bf1c82af 100644 >> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi >> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi >> @@ -5164,6 +5164,146 @@ cci3_i2c1: i2c-bus@1 { >> }; >> }; >> >> + csiphy0: phy@ac9c000 { >> + compatible = "qcom,sa8775p-csi2-phy"; >> + reg = <0x0 0x0ac9c000 0x0 0x2000>; > ... > >> + csiphy3: phy@aca2000 { >> + compatible = "qcom,sa8775p-csi2-phy"; > > phy@ac9c000 through phy@aca2000 nodes precede the existing > isp@ac78000 node. > Sort CSIPHY nodes by unit-address numerically. > >> + reg = <0x0 0x0aca2000 0x0 0x2000>; >> + >> + clocks = <&camcc CAM_CC_CSIPHY3_CLK>, >> + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; >> + clock-names = "core", >> + "timer"; >> + >> + interrupts = ; >> + >> + operating-points-v2 = <&csiphy_opp_table>; >> + >> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; >> + power-domain-names = "top"; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + }; >> + }; >> + }; >> + >> + csiphy_opp_table: opp-table-csiphy { >> + compatible = "operating-points-v2"; >> + >> + opp-300000000 { >> + opp-hz = /bits/ 64 <300000000>; >> + }; >> + >> + opp-400000000 { >> + opp-hz = /bits/ 64 <400000000>; >> + }; >> + }; >> + >> camss: isp@ac78000 { >> compatible = "qcom,sa8775p-camss"; >> >