From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 42F81EEC3 for ; Sun, 12 Apr 2026 15:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776008897; cv=none; b=aZwXaOtplSPfVjtymysfy/WOxdnMB5q3qEJA0omH08vtrLHs1kmNvkLSVIa4X6jSdcu7X3MyeGVB59Wzw7HeKZSnwEifRm2cGhbaioZsbBrsKK352qrjeSDE1bJgQCiw2fWE8b7RJikpXKbnwQVT7VfnI7vzplh6ri/MgZx/vkc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776008897; c=relaxed/simple; bh=U6ulatf8SqiETTDO0DG0hTsg/mvDE9XwOigkPb7/Q0Y=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=B45371GOzQwfrLSmn6IJy8EQa+Ta7iJnzPFySjs3kgsLvgG5yPhkk9KYkoJwg1u3SLQLuc80oAKIUVDdiWbm1vBcWEE7x1p3KA4/4VfW/NmC8uHtWzRyP7FfVhj7PVm116FogBKyUFTV/oKXbI9gvhrcOIRzUM2ioeNbq/NpOXU= ARC-Authentication-Results:i=1; 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h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=J7jVtXKJI1UM4MuYUEKoiFtM9cuug/gRn7tmfStAiwgJ/v7dkVyBiqWlZk+ADC48F xZFQuSHyhlukoVlbjvq0vBInLB/+je7go0lsNQRj7CBkDG8zrhD4VIxtjRbC58uAcH XS/QBZoNfNKL7qXbN6nzvXjwHOAa1ue3UZVGonmo= Date: Sun, 12 Apr 2026 16:48:10 +0100 From: Yeoreum Yun To: Jie Gan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com Subject: Re: [PATCH v2 2/5] coresight: etm4x: exclude ss_status from drvdata->config Message-ID: References: <20260410074310.2693385-1-yeoreum.yun@arm.com> <20260410074310.2693385-3-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Jie, > > > On 4/10/2026 3:43 PM, Yeoreum Yun wrote: > > The purpose of TRCSSCSRn register is to show status of > > the corresponding Single-shot Comparator Control and input supports. > > That means writable field's purpose for reset or restore from idle status > > not for configuration. > > > > Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps. > > This includes remove TRCSSCRn from configurable item and > > remove saving in etm4_disable_hw(). > > > > Signed-off-by: Yeoreum Yun > > --- > > .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 - > > .../hwtracing/coresight/coresight-etm4x-core.c | 18 +++++------------- > > .../coresight/coresight-etm4x-sysfs.c | 7 ++----- > > drivers/hwtracing/coresight/coresight-etm4x.h | 3 ++- > > 4 files changed, 9 insertions(+), 20 deletions(-) > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > > index c302072b293a..d14d7c8a23e5 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > > @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, > > off_mask = (offset & GENMASK(11, 5)); > > do { > > CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); > > - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); > > CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); > > } while (0); > > } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > index 6443f3717b37..b7abb171f523 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > > @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) > > const struct etmv4_caps *caps = &drvdata->caps; > > return (n < caps->nr_ss_cmp) && caps->nr_pe && > > - (drvdata->config.ss_status[n] & TRCSSCSRn_PC); > > + (caps->ss_status[n] & TRCSSCSRn_PC); > > } > > u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) > > @@ -571,11 +571,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); > > for (i = 0; i < caps->nr_ss_cmp; i++) { > > - /* always clear status bit on restart if using single-shot */ > > - if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) > > - config->ss_status[i] &= ~TRCSSCSRn_STATUS; > > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); > > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); > > + /* always clear status bit on restart if using single-shot */ > > the clear step for the status bit has been removed. but the comment still > here. > > I think we cannot remove the clear step. The hardware requires the STATUS > bit to be cleared before re-arming a single-shot comparator; failing to do > so means the comparator will not fire on the next trace session This one is intended. if you see the patch: + /* always clear status bit on restart if using single-shot */ + etm4x_relaxed_write32(csa, caps->ss_status[i], TRCSSCSRn(i)); cap->ss_status[i] is initialised by etm4_init_arch_data() cleared STATUS & PENDING bit. so the comment is still valid. Thanks. [...] -- Sincerely, Yeoreum Yun