From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D15D1FC7FB for ; Thu, 5 Mar 2026 18:01:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.97.179.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772733668; cv=none; b=ChnYTBFUr8nOUDkXhWeHgUknrKSP+rXiMs74VXxLqHm8XR5S+Mz40kaTeAlvom9LYyCkILt+gq6eZTkHOSSnYCAZoTTTIARZIhPiChSSBp+jj4uxxc0wM952pl3HQ1Xt1g4wMMoDuXt99ZV3TN611XQddUlPWz5HVq38J4XL/2s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772733668; c=relaxed/simple; bh=SAItOOXHqAL9irqblkrpIvkXzW04hPxYbRVec/2OBm0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=XRZdVmJ4wOsr/9CZTKIJjfWjJMdp9U7JCzVsACFDxuLHin/7wsjhd4tbz9GoozFoWBDvz7GxOVwTsr0dy3Buhh7pJcgm+TM5NaXQMslNTh9EWU1vEKlKzYhxcNm3ZsHNzYz9DIPD5KTB5AYi50YGfrograuo/ALe0Qnqr0apc7U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=igalia.com; spf=pass smtp.mailfrom=igalia.com; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b=DPzCFkE0; arc=none smtp.client-ip=213.97.179.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=igalia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=igalia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b="DPzCFkE0" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID:Sender:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=YUr1+sWEO9j5kitoHz+vNz4j+awsJ1fwf/poatsFNbU=; b=DPzCFkE0MC874adOXYhljT3y3s 1r4WzOqbGBJUT1HrX43ZOiB35t7xvcy21s7NgHX8freBwrlCwrPbE9B8RhEuG4rzc1laiHDMyVixZ gSbR9wAk9tp9p/lCQ+m8IyJDgKlhA/29iJX7WLvGMVXKw7xo+AHiSk3NC25kOGhiBDvn7L5qutJx3 +9AuuHd8ScbmTcYOxBC+m17yRBb1AlgTKDxAqwfWBd7wwzJMrO3EKKim1NbT0vTxQ5xirUYTRW7X6 M/JQ+dmICa+pLHgEBlHHSZaIQB+8c7bDavGbkdmlQumc5F07SPUuqnzM5wE8RgSHJXfwM2vDf3gz5 IXcTiHyA==; Received: from [186.208.68.119] (helo=[192.168.18.14]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_128_GCM:128) (Exim) id 1vyD0G-009Tnn-Kz; Thu, 05 Mar 2026 19:00:52 +0100 Message-ID: Date: Thu, 5 Mar 2026 15:00:47 -0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RESEND v2] drm/amdgpu: Fix kernel-doc comments for some LUT properties To: Cristian Ciocaltea , Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= , David Airlie , Simona Vetter , Harry Wentland Cc: kernel@collabora.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alex Hung References: <20260305-amdgpu-fix-kdoc-lut-v2-1-37947aca68e8@collabora.com> Content-Language: en-US From: Melissa Wen In-Reply-To: <20260305-amdgpu-fix-kdoc-lut-v2-1-37947aca68e8@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit + cc: Alex Hung Hi Alex H., Can you apply this patch? Thanks, Melissa On 05/03/2026 08:16, Cristian Ciocaltea wrote: > The following members of struct amdgpu_mode_info do not have valid > references in the related kernel-doc sections: > > - plane_shaper_lut_property > - plane_shaper_lut_size_property, > - plane_lut3d_size_property > > Correct all affected comment blocks. > > Fixes: f545d82479b4 ("drm/amd/display: add plane shaper LUT and TF driver-specific properties") > Fixes: 671994e3bf33 ("drm/amd/display: add plane 3D LUT driver-specific properties") > Reviewed-by: Melissa Wen > Signed-off-by: Cristian Ciocaltea > --- > Changes in v2: > - Collected R-b tag from Melissa > - Rebased onto latest drm-misc-next > - Link to v1: https://lore.kernel.org/r/20250823-amdgpu-fix-kdoc-lut-v1-1-306bcad41267@collabora.com > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h > index dc8d2f52c7d6..e244c12ceb23 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h > @@ -368,15 +368,15 @@ struct amdgpu_mode_info { > > struct drm_property *plane_ctm_property; > /** > - * @shaper_lut_property: Plane property to set pre-blending shaper LUT > - * that converts color content before 3D LUT. If > - * plane_shaper_tf_property != Identity TF, AMD color module will > + * @plane_shaper_lut_property: Plane property to set pre-blending > + * shaper LUT that converts color content before 3D LUT. > + * If plane_shaper_tf_property != Identity TF, AMD color module will > * combine the user LUT values with pre-defined TF into the LUT > * parameters to be programmed. > */ > struct drm_property *plane_shaper_lut_property; > /** > - * @shaper_lut_size_property: Plane property for the size of > + * @plane_shaper_lut_size_property: Plane property for the size of > * pre-blending shaper LUT as supported by the driver (read-only). > */ > struct drm_property *plane_shaper_lut_size_property; > @@ -400,10 +400,10 @@ struct amdgpu_mode_info { > */ > struct drm_property *plane_lut3d_property; > /** > - * @plane_degamma_lut_size_property: Plane property to define the max > - * size of 3D LUT as supported by the driver (read-only). The max size > - * is the max size of one dimension and, therefore, the max number of > - * entries for 3D LUT array is the 3D LUT size cubed; > + * @plane_lut3d_size_property: Plane property to define the max size > + * of 3D LUT as supported by the driver (read-only). The max size is > + * the max size of one dimension and, therefore, the max number of > + * entries for 3D LUT array is the 3D LUT size cubed. > */ > struct drm_property *plane_lut3d_size_property; > /** > > --- > base-commit: be4cd2a13a31496c7fb9e46a244c4391b8b7cf31 > change-id: 20250823-amdgpu-fix-kdoc-lut-357db8b57fee