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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA3NCBTYWx0ZWRfX7drhikGLxcrW M8veGok3AyJDKYLu1jwV2a2eSSHSuDhs7q1/VsqYakfqslTzueW9iR8FdNCYPdQLBtr3+jDH5y6 XSQlpgLETfAPXoV3kzJ8PyrOoWNb77A= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA3NCBTYWx0ZWRfX4pnFilgTw3E3 MiBZx0/O16di4NWox6gaRvcAXqxt09i1ExOKkO9Zgh7bWWiRwTeaNk7RuH32KEnRJ6ycFWMth24 OXIjzehwAwKMAR5DZO3ANnKfvrzEpD/2ZRiXz5rYEirqYPQZL4vO06RSeDc57/6LGqMWdQftkQg 5PZlY4KCCrok8nuT9AcW7RtFE7LZyurle9X3+mNKmFmXDlHOhWqoXwpluz1x/wYjfSWKsNNlGEb 6kQI4M1oMthf2vi09waTwSGa0nkxN9GYZDIKp2DCnUw3BVlBb6o3sW0EnEwEj/jB5IzVzp8PHlu leL3uoDn+jY2sHslbiU/Yoi+AdJF6PNTBTT1eBq7OuzdZSpID64IYQXnHJ2EeQOamL859hPIfxJ yv3JBPZuklEiTSLVqw1zYMvVlWv0/Gnyi5JDDQz60pVL+k8o3L2SNBol0MDdZovdcp4QSDlXlAA 0tKJ+Ms7yYM4Wlq/RJQ== X-Proofpoint-GUID: 7lzb1LPN19UWRwxtJxdzE0BQlg2IRM5h X-Authority-Analysis: v=2.4 cv=cefiaHDM c=1 sm=1 tr=0 ts=6a4238cc cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=zBfHOgCXiaqlRJpMRBUA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-ORIG-GUID: 7lzb1LPN19UWRwxtJxdzE0BQlg2IRM5h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290074 On 6/29/26 7:05 AM, Qiang Yu wrote: > On Wed, Jun 17, 2026 at 01:19:49PM +0200, Konrad Dybcio wrote: >> On 5/19/26 7:47 AM, Qiang Yu wrote: >>> Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and >>> PCIe3b as consumers of that shared PHY provider instead of separate PHY >>> nodes. >>> >>> Update the DTS wiring to: >>> - point GCC PCIe3A/3B pipe parents to the shared PHY clock outputs >>> - add PCIe3a controller node and route PCIe3a/PCIe3b port phys to >>> &pcie3_phy using two-cell PHY arguments >>> - configure the shared PHY node with link-mode and dual pipe outputs >>> >>> Use QMP_PCIE_GLYMUR_MODE_* dt-binding macros for mode selection. >>> >>> Signed-off-by: Qiang Yu >>> --- >> >> [...] >> >>> + pcie3a: pci@1c10000 { >>> + device_type = "pci"; >>> + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; >>> + reg = <0x0 0x01c10000 0x0 0x3000>, >>> + <0x0 0x70000000 0x0 0xf20>, >>> + <0x0 0x70000f40 0x0 0xa8>, >>> + <0x0 0x70001000 0x0 0x4000>, >>> + <0x0 0x70100000 0x0 0x100000>, >>> + <0x0 0x01c13000 0x0 0x1000>; >>> + reg-names = "parf", >>> + "dbi", >>> + "elbi", >>> + "atu", >>> + "config", >>> + "mhi"; >>> + #address-cells = <3>; >>> + #size-cells = <2>; >>> + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, >>> + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>, >>> + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>, >>> + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>; >>> + >>> + bus-range = <0 0xff>; >>> + >>> + dma-coherent; >>> + >>> + linux,pci-domain = <3>; >>> + num-lanes = <8>; >> >> Is it fine to keep num-lanes 8 here even for configurations with >> bifurcated PHY? >> >> I would assume so, given essentially this is a x8 host, whose 4 >> lanes may simply be effectively NC >> > Actually, on existing platforms, the PCIe3a and PCIe3b controllers are > never enabled at the same time. When PCIe3a is exposed, it is always in an > x8 slot. But if we have a x4+x4 platform in future, we can simply override > num-lanes to 4 in the board.dts. My question is whether that will be necessary - if yes, sure, we can do it, but if not, we can conclude on this early and not have to fight over it in a couple months Konrad