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4.63) (envelope-from ) id 1kQQTu-0006IG-9P; Thu, 08 Oct 2020 00:36:54 -0700 Subject: Re: [PATCH v4 2/4] dt-bindings: mmc: Add uhs-gpio for Keem Bay UHS-1 Support To: muhammad.husaini.zulkifli@intel.com, adrian.hunter@intel.com, michal.simek@xilinx.com, andriy.shevchenko@intel.com, ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: lakshmi.bai.raja.subramanian@intel.com, wan.ahmad.zainie.wan.mohamad@intel.com, arnd@arndb.de References: <20201008020936.19894-1-muhammad.husaini.zulkifli@intel.com> <20201008020936.19894-3-muhammad.husaini.zulkifli@intel.com> From: Michal Simek Autocrypt: addr=michals@xilinx.com; keydata= xsFNBFFuvDEBEAC9Amu3nk79+J+4xBOuM5XmDmljuukOc6mKB5bBYOa4SrWJZTjeGRf52VMc howHe8Y9nSbG92obZMqsdt+d/hmRu3fgwRYiiU97YJjUkCN5paHXyBb+3IdrLNGt8I7C9RMy svSoH4WcApYNqvB3rcMtJIna+HUhx8xOk+XCfyKJDnrSuKgx0Svj446qgM5fe7RyFOlGX/wF Ae63Hs0RkFo3I/+hLLJP6kwPnOEo3lkvzm3FMMy0D9VxT9e6Y3afe1UTQuhkg8PbABxhowzj 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X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB6465 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08. 10. 20 4:09, muhammad.husaini.zulkifli@intel.com wrote: > From: Muhammad Husaini Zulkifli > > Add DT bindings of uhs-gpio for Keem Bay SOC UHS Mode Support > > Signed-off-by: Muhammad Husaini Zulkifli > --- > Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml > index 58fe9d02a781..320566a673f0 100644 > --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml > +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml > @@ -83,7 +83,7 @@ properties: > - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller > description: > For this device it is strongly suggested to include > - arasan,soc-ctl-syscon. > + arasan,soc-ctl-syscon and uhs-gpio. > - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller > description: > For this device it is strongly suggested to include > @@ -152,6 +152,11 @@ properties: > description: > The MIO bank number in which the command and data lines are configured. > > + uhs-gpio: > + description: > + The power mux input will be configure using the GPIO provided > + to generate either 1.8v or 3.3v output. > + > dependencies: > clock-output-names: [ '#clock-cells' ] > '#clock-cells': [ clock-output-names ] > @@ -300,4 +305,5 @@ examples: > clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, > <&scmi_clk KEEM_BAY_PSS_SD0>; > arasan,soc-ctl-syscon = <&sd0_phy_syscon>; > + uhs-gpio = <&pca0 17 0>; > }; > Acked-by: Michal Simek Thanks, Michal