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Mon, 08 Sep 2025 09:15:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHZF1OPxZnSURBZkaB/X4pj0b/Fs/TUocy/fiORRAwfDENjJPxq3DAYNP2im4uK6ps4zcHOGQ== X-Received: by 2002:a17:90b:48d2:b0:32b:cba3:6361 with SMTP id 98e67ed59e1d1-32d43f76b78mr10340134a91.26.1757348140791; Mon, 08 Sep 2025 09:15:40 -0700 (PDT) Received: from [10.91.118.43] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32b948d5471sm6213558a91.3.2025.09.08.09.15.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Sep 2025 09:15:40 -0700 (PDT) Message-ID: Date: Mon, 8 Sep 2025 21:45:33 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/16] drm/msm/adreno: Add fenced regwrite support To: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Neil Armstrong References: <20250908-ifpc-support-v2-0-631b1080bf91@oss.qualcomm.com> <20250908-ifpc-support-v2-7-631b1080bf91@oss.qualcomm.com> <59ac7827-6258-4268-8b71-4cbcbad859db@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <59ac7827-6258-4268-8b71-4cbcbad859db@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTA2MDAzOCBTYWx0ZWRfXxkiNaNfIGqRl MyMP1RlwK321M2vF1sz0DyIx/5qkcx32SSvl1efwzLex7oKj2XyVd5I10m4De+U8cbaR1njcMtL 1eZRxhSsZI3wmBplpYRiXgzbFLNuF3dk7ryXxEziMBEp0TiJ+vpXsmiiJgS7e2vMzRR+0Ya8yiM LQd8DAuVK/W0a5G3NWzoVH7CTkxJ+j74xJYKWClcUXUFZF+RiukEmft+TUdph8Q4v7NXJURqR4x VMzQxCanWxpmKs2zVsl2/j14weAjMyrMyYy+4oWgec3nNCq00AqS6m9p6nYdyL96Xz8GQ9Bkgmg XLgMHNQ2yBhJIMk3ekA+puhuYxA5GF8v5w5dEnZdEtrWclSxsTriGqZcGFxTmUKvQhiUuYejOAi eIVkvw3O X-Authority-Analysis: v=2.4 cv=J66q7BnS c=1 sm=1 tr=0 ts=68bf012e cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=Npwa9MXoYRiG9O3kBDcA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: mO2rynJYHY2km7DYCSSC157CXrelUyQa X-Proofpoint-ORIG-GUID: mO2rynJYHY2km7DYCSSC157CXrelUyQa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-08_06,2025-09-08_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 spamscore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509060038 On 9/8/2025 9:07 PM, Konrad Dybcio wrote: > On 9/8/25 10:27 AM, Akhil P Oommen wrote: >> There are some special registers which are accessible even when GX power >> domain is collapsed during an IFPC sleep. Accessing these registers >> wakes up GPU from power collapse and allow programming these registers >> without additional handshake with GMU. This patch adds support for this >> special register write sequence. >> >> Signed-off-by: Akhil P Oommen >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 80 ++++++++++++++++++++++++++++++- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + >> drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 20 ++++---- >> 3 files changed, 90 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> index 45dd5fd1c2bfcb0a01b71a326c7d95b0f9496d99..a63dad80ef461da45d5c41a042ed4f19d8282ef5 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >> @@ -16,6 +16,84 @@ >> >> #define GPU_PAS_ID 13 >> >> +static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) >> +{ >> + /* Success if !writedropped0/1 */ >> + if (!(status & mask)) >> + return true; >> + >> + udelay(10); >> + >> + /* Try to update fenced register again */ >> + gpu_write(gpu, offset, value); >> + >> + /* We can't do a posted write here because the power domain could be >> + * in collapse state. So use the heaviest barrier instead >> + */ >> + mb(); >> + return false; >> +} >> + >> +static int fenced_write(struct a6xx_gpu *a6xx_gpu, u32 offset, u32 value, u32 mask) >> +{ >> + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; >> + struct msm_gpu *gpu = &adreno_gpu->base; >> + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; >> + u32 status; >> + >> + gpu_write(gpu, offset, value); >> + >> + /* Nothing else to be done in the case of no-GMU */ >> + if (adreno_has_gmu_wrapper(adreno_gpu)) >> + return 0; >> + >> + /* We can't do a posted write here because the power domain could be >> + * in collapse state. So use the heaviest barrier instead >> + */ > > I'm not sure I follow - what's the relationship between the write being > posted and the power domain being collapsed (i.e. the hw not being > powered on)? > > Are you trying to get rid of the delay that could happen between this > write leaving the CPU and arriving at the GPU (which would then be > woken up), so that the 1ms poll below has greater chance to succeed > because of how these "special registers" work? We should strictly ensure that the GX register write is posted first (it could be posted to the hw or dropped by the fence hw). Otherwise the fence status register (in CX domain) might incorrectly report that the register write went through. Ideally, we should do a posted write here, but we can't do that due to IFPC. A full barrier (DSB SY) will ensure this ordering requirement. Another motivation here is to align closely with the downstream sequence which uses a similar barrier. It will be a super painful debug if this sequence miss a register write. -Akhil. > > Konrad