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Thu, 15 Nov 2018 02:08:44 -0800 (PST) Subject: Re: [RFC v1 0/7] Meson8b: make the CPU clock mutable To: Martin Blumenstingl , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jbrunet@baylibre.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org References: <20181114225725.2821-1-martin.blumenstingl@googlemail.com> From: Neil Armstrong Openpgp: preference=signencrypt Autocrypt: addr=narmstrong@baylibre.com; prefer-encrypt=mutual; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKE5laWwgQXJtc3Ryb25nIDxuYXJtc3Ryb25nQGJheWxpYnJlLmNvbT7CwHsEEwEKACUC GyMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheABQJXDO2CAhkBAAoJEBaat7Gkz/iubGIH/iyk RqvgB62oKOFlgOTYCMkYpm2aAOZZLf6VKHKc7DoVwuUkjHfIRXdslbrxi4pk5VKU6ZP9AKsN NtMZntB8WrBTtkAZfZbTF7850uwd3eU5cN/7N1Q6g0JQihE7w4GlIkEpQ8vwSg5W7hkx3yQ6 2YzrUZh/b7QThXbNZ7xOeSEms014QXazx8+txR7jrGF3dYxBsCkotO/8DNtZ1R+aUvRfpKg5 ZgABTC0LmAQnuUUf2PHcKFAHZo5KrdO+tyfL+LgTUXIXkK+tenkLsAJ0cagz1EZ5gntuheLD YJuzS4zN+1Asmb9kVKxhjSQOcIh6g2tw7vaYJgL/OzJtZi6JlIXOwE0ETVkGzwEIALyKDN/O GURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYpQTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXM coJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hi SvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY4yG6xI99NIPEVE9lNBXBKIlewIyVlkOa YvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoMMtsyw18YoX9BqMFInxqYQQ3j/HpVgTSv mo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUXoUk33HEAEQEAAcLAXwQYAQIACQUCTVkG zwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfnM7IbRuiSZS1unlySUVYu3SD6YBYnNi3G 5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa33eDIHu/zr1HMKErm+2SD6PO9umRef8V8 2o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCSKmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+ RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJ C3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTTQbM0WUIBIcGmq38+OgUsMYu4NzLu7uZF Acmp6h8g Organization: Baylibre Message-ID: Date: Thu, 15 Nov 2018 11:08:43 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20181114225725.2821-1-martin.blumenstingl@googlemail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin, On 14/11/2018 23:57, Martin Blumenstingl wrote: > This allows changing the CPU clock on the 32-bit Amlogic Meson SoCs > (Meson8, Meson8b and Meson8m2). > CPU frequency scaling will be enabled with a separate series by adding > the CPU clock and the OPP tables to meson8.dtsi and meson8b.dtsi. > > While changing the CPU frequency (sys_pll or any of it's post-dividers) > we need to run the CPU clock off the XTAL clock. Otherwise the system > will lock up because we need to disable the sys_pll to change it's > rate. > > This also makes the clk-pll's .enable hook a no-op if the clock is > already enabled. Otherwise we're getting lockups when calling the > first clk_{prepare_}enable on the sys_pll or any of it's children (as > the CCF propagates the enable event up to the sys_pll). This is because > the .enable hook unconditionally disables and enables the clock. > However, we can't disable that clock (not even temporarily) if the CPU > is running off sys_pll. > > Additionally this adds support for more M/N combinations in sys_pll to > achieve all of the OPPs on Meson8b and all OPPs <= 1608 MHz on Meson8 > and Meson8m2. > > Compared to Amlogic's 3.10 kernel there's one notable difference: we > are actually allowing changes to the sys_pll. Amlogic's kernel sets > sys_pll to a fixed rate during boot and then uses a timer generate a > "virtual clock rate" by toggling between various dividers (for example: > sys_pll is set to 1536MHz. to achieve 1008MHz they are toggling every > 2500us between 1536MHZ and 768MHz so the average over example one second> is 1008MHz). > I could reproduce any situation where changing sys_pll failed (for > example due to high temperature). To prove that I ran "stress --cpu 4" > for multiple hours and then cycled through all available CPU > frequencies (while keeping "stress" running in the background). This > worked fine on my Meson8b Odroid-C1 and EC-100 boards as well as my > Meson8m2 board. > > > Martin Blumenstingl (7): > clk: meson: meson8b: run from the XTAL when changing the CPU frequency > clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel > clk: meson: clk-pll: check if the clock is already enabled > clk: meson: clk-pll: add the is_enabled function in the clk_ops > clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL > clk: meson: meson8b: add support for more M/N values in sys_pll > clk: meson: meson8b: allow changing the CPU clock tree > > drivers/clk/meson/clk-pll.c | 23 +++++++++ > drivers/clk/meson/meson8b.c | 94 +++++++++++++++++++++++++++++++++---- > 2 files changed, 108 insertions(+), 9 deletions(-) > I suppose it depends on the fixes you sent earlier ? Anyway, resend it without RFC and by squashing patch 4 in 3 and address the small comment issue and I'll take it for 4.21 ! Thanks, Neil