From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: ARC-Seal: i=1; a=rsa-sha256; t=1516540002; cv=none; d=google.com; s=arc-20160816; b=ROsTTq4bjVahkogzt5Ck1Abtexo+E0RJT16ux7H9yS9Yq9B9p+dN50+JMuQeBv6MEk Gja2rY9LXRHAnokD8207n/X3/yyZQqr0QqT7tKlivjcetxPFeOWKkLU7el0eNtR8B4CH /yKZogDG/jdvguVlIx8ZFCdinz5ZbPcBdMtihKXRxHSItaFmGIpjXkCPYfRdiRpP7wK8 YDOL3wnlFpw9bmOhYS9FsabqsF71VARcO5gA8eV7uPjtMlQh3DgTiuJBQUAgybEwEtPd 4vxxmFFykgHSNFCIGa6kFwjmOmRlVOnnWzARzKAqcyV91IOGPsW+ficr7WZKRCPbsVTA EjWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:content-language:in-reply-to:mime-version :user-agent:date:message-id:from:references:to:subject :arc-authentication-results; bh=Ud5hz6rFmqx8IdwfsNqUVo7ABE1+8WFZoprY/lL9cwg=; b=UBhXiEaAck+YIBy6NE/4JM7wj8SNVU9U06o/88STH02Lhzmww5Dh/d1UulA0PzPTHy ZVBWywfk/fAEKvXMNdtCgpq30coVUpUZrMoouRlJVgrLp9ZjAb6QDifL6TfdOqJm1iAg bDrCf6kJ9maxJzTWuY0+ywnVt83yjQsnFMi3iTVVY5i4Aa92X4R69HN7EgBpsYrEOr50 kgwbuiB04r99tm1VF+xVhd+5CTsSB1Qcmk79soMaVEQYl7Kx4FIIzzJBOauQBFbDOwxm S0xPX3NzidYno13tHoNQASjcY600gv7mrIiLNqC6M3/wR4aUs4hKoQSbTbUBVmcFQ4DV nVLg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of jirislaby@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jirislaby@gmail.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of jirislaby@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=jirislaby@gmail.com X-Google-Smtp-Source: AH8x226xs8ps8eqrVH626LlGpiGWPxsYYTUgnA7sFsFmsrgJXP1FpOU6BDcaDb8eZUOlRmcKv3zRNg== Subject: Re: [PATCH v2 3/8] x86/msr: Add definitions for new speculation control MSRs To: David Woodhouse , arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org References: <1516528149-9370-1-git-send-email-dwmw@amazon.co.uk> <1516528149-9370-4-git-send-email-dwmw@amazon.co.uk> From: Jiri Slaby Message-ID: Date: Sun, 21 Jan 2018 14:06:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 MIME-Version: 1.0 In-Reply-To: <1516528149-9370-4-git-send-email-dwmw@amazon.co.uk> Content-Type: text/plain; charset=iso-8859-2 Content-Language: en-GB Content-Transfer-Encoding: 7bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590195051986587278?= X-GMAIL-MSGID: =?utf-8?q?1590207449961143725?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 01/21/2018, 10:49 AM, David Woodhouse wrote: > Add MSR and bit definitions for SPEC_CTRL, PRED_CMD and ARCH_CAPABILITIES. > > See Intel's 336996-Speculative-Execution-Side-Channel-Mitigations.pdf > > Signed-off-by: David Woodhouse > --- > arch/x86/include/asm/msr-index.h | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index fa11fb1..3e50463 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -42,6 +42,13 @@ > #define MSR_PPIN_CTL 0x0000004e > #define MSR_PPIN 0x0000004f > > +#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ > +#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ > +#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ > + > +#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ > +#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ > + > #define MSR_IA32_PERFCTR0 0x000000c1 > #define MSR_IA32_PERFCTR1 0x000000c2 > #define MSR_FSB_FREQ 0x000000cd > @@ -60,6 +67,10 @@ > #define MSR_IA32_BBL_CR_CTL 0x00000119 > #define MSR_IA32_BBL_CR_CTL3 0x0000011e > > +#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a > +#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ > +#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ Is there any reason why all 3 are not properly sorted? 0x04e > 0x048 0x119 > 0x10a > #define MSR_IA32_SYSENTER_CS 0x00000174 > #define MSR_IA32_SYSENTER_ESP 0x00000175 > #define MSR_IA32_SYSENTER_EIP 0x00000176 > thanks, -- js suse labs