Re: [PATCH v2] riscv: add tracepoints for page fault

[Zhu Hengbo <zhuhengbo@iscas.ac.cn>]

On 2024/7/17 22:55, Matthew Wilcox wrote:
> On Wed, Jul 17, 2024 at 08:27:19AM +0000, Zhu Hengbo wrote:
>> +	TP_STRUCT__entry(
>> +		__field(unsigned long, address)
>> +		__field(unsigned long, epc)
>> +		__field(unsigned long, cause)
>> +	),
>> +
>> +	TP_fast_assign(
>> +		__entry->address	= regs->badaddr;
>> +		__entry->epc		= regs->epc;
>> +		__entry->cause		= regs->cause;
>> +	),
>> +
>> +	TP_printk("user page fault, address=%ps epc=%ps cause=0x%lx",
>> +			(void *)__entry->address, (void *)__entry->epc,
>> +			__entry->cause)
> What is "epc"?  You've made this gratuitously different from x86.
> Never do that.  Always copy what somebody else has done unless you have
> a good reason to be different.

“epc” stands for Exception Program Counter, which keeps track of where the CPU is within the code. It is the same as the Instruction Pointer in x86.

For example, here is the encapsulation of accessing the instruction pointer in risc-v:

    /* Helpers for working with the instruction pointer */
    static inline unsigned long instruction_pointer(struct pt_regs *regs)
    {
        return regs->epc;
    }