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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e53d4bdaf7sm42339974eec.25.2026.04.27.08.05.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 08:05:16 -0700 (PDT) Date: Mon, 27 Apr 2026 08:05:14 -0700 From: Mike Tipton To: Vivek Aknurwar Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: Re: [PATCH v2 7/7] clk: qcom: Add support for global clock controller on Hawi Message-ID: References: <20260409-clk-hawi-v2-0-c7a185389d9a@oss.qualcomm.com> <20260409-clk-hawi-v2-7-c7a185389d9a@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260409-clk-hawi-v2-7-c7a185389d9a@oss.qualcomm.com> X-Proofpoint-ORIG-GUID: NPIZxI2NY_Yd2PQyRzkfKR_YXs_0dYIl X-Authority-Analysis: v=2.4 cv=Xba5Co55 c=1 sm=1 tr=0 ts=69ef7b2e cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=7t-CPqBheUaPz9YIfAcA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: NPIZxI2NY_Yd2PQyRzkfKR_YXs_0dYIl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDE1OSBTYWx0ZWRfX8RgY1j5wM3vP 5zpaCjguH7IsRxQOaM6dgI3WY4zByPNz7ve/oNKLUrFFjvtSo9YBuuLsXdH0LQxEBl6nMQlapn1 3jqI/0dtwOGMBcj3vbJa8f8mZ76izrsN+DKW4cOI4jpQf1yJd1WPwZol5z/KcJ6l04F3+s1ajdx C7cqQaPmL/TM3LFvFATzaPxsMkjvhaZqF/9sq0DdYWQM7unHEG/ICWxX5TJAqSy4X6ZaZQ/a3vd dEwZyF6Qe206B4dKxZCQyw6+L/3WNfm6SUQmoNi4wmLiFldGnTcya0mQ3AxV5JFiDn+lJWP4gVj 1V3iVkmtyTgZqoBFPHaVorGE1e5O8xtsupJWayB+u+ADffk9wSGLm8t1DypkRSCASLLFiIHjGAC 5OJ4qqiShGh2R48JBaj4R2Ms4rXflCVUyDD9jlM6u8TVNXSKsG9K/JYjtGoH/lPs+SugFM9hUZV SVTtdOAGWXCz8rT1FwA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-27_04,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 suspectscore=0 phishscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270159 On Thu, Apr 09, 2026 at 01:51:41PM -0700, Vivek Aknurwar wrote: > Add support for the global clock controller (GCC) on the > Qualcomm Hawi SoC. > > Reviewed-by: Taniya Das > Reviewed-by: Konrad Dybcio > Signed-off-by: Vivek Aknurwar > --- > drivers/clk/qcom/Kconfig | 9 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-hawi.c | 3657 +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 3667 insertions(+) [..] > + > +static u32 gcc_hawi_critical_cbcrs[] = { This should be const now since qcom_cc_driver_data::clk_cbcrs was recently made const. > + 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ > + 0x26004, /* GCC_CAMERA_AHB_CLK */ > + 0x26028, /* GCC_CAMERA_RSC_CORE_CLK */ > + 0x26024, /* GCC_CAMERA_XO_CLK */ > + 0x9f004, /* GCC_EVA_AHB_CLK */ > + 0x9f018, /* GCC_EVA_XO_CLK */ > + 0x71004, /* GCC_GPU_CFG_AHB_CLK */ > + 0x7101c, /* GCC_GPU_RSC_CORE_CLK */ > + 0x67084, /* GCC_PCIE_1_RSC_CORE_CLK */ > + 0x43014, /* GCC_PCIE_LINK_XO_CLK */ > + 0x6b088, /* GCC_PCIE_RSC_CORE_CLK */ > + 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ > + 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ > + 0x32004, /* GCC_VIDEO_AHB_CLK */ > + 0x32028, /* GCC_VIDEO_XO_CLK */ > +}; [..] > + > +static struct qcom_cc_driver_data gcc_hawi_driver_data = { This should be const now since qcom_cc_desc::driver_data was recently made const. > + .clk_cbcrs = gcc_hawi_critical_cbcrs, > + .num_clk_cbcrs = ARRAY_SIZE(gcc_hawi_critical_cbcrs), > + .dfs_rcgs = gcc_hawi_dfs_clocks, > + .num_dfs_rcgs = ARRAY_SIZE(gcc_hawi_dfs_clocks), > + .clk_regs_configure = clk_hawi_regs_configure, > +}; > + > +static const struct qcom_cc_desc gcc_hawi_desc = { > + .config = &gcc_hawi_regmap_config, > + .clks = gcc_hawi_clocks, > + .num_clks = ARRAY_SIZE(gcc_hawi_clocks), > + .resets = gcc_hawi_resets, > + .num_resets = ARRAY_SIZE(gcc_hawi_resets), > + .gdscs = gcc_hawi_gdscs, > + .num_gdscs = ARRAY_SIZE(gcc_hawi_gdscs), > + .use_rpm = true, > + .driver_data = &gcc_hawi_driver_data, > +}; > + Thanks, Mike