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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2de8eb84813sm5427848eec.18.2026.04.15.20.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Apr 2026 20:24:48 -0700 (PDT) Date: Wed, 15 Apr 2026 20:24:46 -0700 From: Qiang Yu To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 5/5] arch: arm64: dts: qcom: Add support for PCIe3a Message-ID: References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> <20260412-glymur_gen5x8_phy_0413-v3-5-affcebc16b8b@oss.qualcomm.com> <20260415-pragmatic-termite-of-attraction-3dbab5@quoll> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260415-pragmatic-termite-of-attraction-3dbab5@quoll> X-Proofpoint-GUID: I7fcqF-zyQ71vJ4IXnwo4hhjhX2jQPoe X-Proofpoint-ORIG-GUID: I7fcqF-zyQ71vJ4IXnwo4hhjhX2jQPoe X-Authority-Analysis: v=2.4 cv=GP441ONK c=1 sm=1 tr=0 ts=69e05682 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=u3NGOs1Tg4bIGv4jLNkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE2MDAyOSBTYWx0ZWRfX8Xtqb+7n1vYH 2TlNSjl2CTOVRHSZeCidpfTOdu39GLCrhAQcHWUpbQpgB/Pj9YasJ1oazv6qaYqoeqPdDY4hHaO Ody3p9ItLLZ3q3WaBQqU3m96zJqll4LOSWdDl892P6QwXVIMqxcbn6d+j1vkt58ze5bmz33fzsv GOBiRW5yEv1IeUL8aP2E1sWcYkIKyMshnZsNoVMJ0VfQPcYp1/hRXCB/+o35LZK8/GSNMOecbE3 LiVK2mlG6aq/9H4pHa7Z6kLq0aI0ZCoVlXd6qY++TP6kBtAyAhM4xz9aBijGk3uXsfmGZlLk/lJ b1OfGLDUsoa+qEKUrWvYVLNUiRzmyxos+erWbBfTVBDD6fHbCZ0vWJBWLQ3a7MwRHMdcycMLTxZ EZtmgsg+7Tc61ncCEc5Bc4w5fIBKNxLd0qQgr04/P8JE6xjkuljzdSnlkc80yqXqZ1cRovTCtWk UDdCK0FWEBrM3edlWsQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-16_01,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604160029 On Wed, Apr 15, 2026 at 09:44:15AM +0200, Krzysztof Kozlowski wrote: > On Sun, Apr 12, 2026 at 11:26:00PM -0700, Qiang Yu wrote: > > Describe PCIe3a controller and PHY. Also add required system resources > > like regulators, clocks, interrupts and registers configuration for PCIe3a. > > > > Signed-off-by: Qiang Yu > > subject: drop arch. > > Please use subject prefixes matching the subsystem. You can get them for > example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory > your patch is touching. For bindings, the preferred subjects are > explained here: > https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters > Thanks for pointing me the link. I’ll drop arch: in next version. > > --- > > arch/arm64/boot/dts/qcom/glymur.dtsi | 316 ++++++++++++++++++++++++++++++++++- > > 1 file changed, 315 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi > > index f23cf81ddb77a4138deeb4e00dd8b316930a2feb..c15f87c37ecbad72076a6c731f4959a1a8bd8425 100644 > > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi > > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi > > @@ -736,7 +736,7 @@ gcc: clock-controller@100000 { > > <0>, /* USB 2 Phy PCIE PIPEGMUX */ > > <0>, /* USB 2 Phy PIPEGMUX */ > > <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ > > - <0>, /* PCIe 3a */ > > + <&pcie3a_phy>, /* PCIe 3a */ > > <&pcie3b_phy>, /* PCIe 3b */ > > <&pcie4_phy>, /* PCIe 4 */ > > <&pcie5_phy>, /* PCIe 5 */ > > @@ -3640,6 +3640,320 @@ pcie3b_port0: pcie@0 { > > }; > > ... > > > > + pcie3a_phy: phy@f00000 { > > Same comment as before. > The existing PCIe/PHY nodes are not strictly ordered by address. Current order is: - pcie4: pci@1bf0000 - pcie4_phy: phy@1bf6000 - pcie5: pci@1b40000 - pcie5_phy: phy@1b50000 - pcie6: pci@1c00000 - pcie6_phy: phy@1c06000 - pcie3b: pci@1b80000 - pcie3a: pci@1c10000 (added in this patch) - pcie3a_phy: phy@f00000 (added in this patch) - pcie3b_phy: phy@f10000 Do you want me to reorder these nodes to follow strict address order? - Qiang Yu > Best regards, > Krzysztof >