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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2de8c606222sm7203340eec.8.2026.04.15.20.56.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Apr 2026 20:56:16 -0700 (PDT) Date: Wed, 15 Apr 2026 20:56:15 -0700 From: Qiang Yu To: Konrad Dybcio , Wesley Cheng Cc: Bjorn Andersson , Taniya Das , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , johan@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH RFC 3/4] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper Message-ID: References: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com> <20260331-qref_vote-v1-3-3fd7fbf87864@oss.qualcomm.com> <3d4a12f1-a9ba-4955-b018-f1c271aab766@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <3d4a12f1-a9ba-4955-b018-f1c271aab766@oss.qualcomm.com> X-Proofpoint-GUID: KOU3zxfifkOFaJirCPByPCcGSOjWT69O X-Proofpoint-ORIG-GUID: KOU3zxfifkOFaJirCPByPCcGSOjWT69O X-Authority-Analysis: v=2.4 cv=GP441ONK c=1 sm=1 tr=0 ts=69e05de2 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=bHU4chEc-QCxAg9O244A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE2MDAzNCBTYWx0ZWRfX+LOoqW8Yhfea jMKAJVzOKyEM63k6lEmkJL6mB20Pqf9RHHKvK5O/S+BG/u+MvR5DBIbIqkS1INuxLkjurReDnO9 eddDtLzGhLlR0m1AR3wWGHIjxv8moeDjT3OQksasbgY+dpfFe33q6QaySED9aEkkUYpL3YPEis/ 9Csy5aCjw59cN7h9WY7LFT/cu0sLHzft1n7qJ7NNaXEIPuLgQCiqRzxFzRfdaaBoVAe2OiUwdTL KXuGOpncuvRO+8KYsTxYpqFI9t+z6db7I1w3B5gdM+K7Li1uBL5paPkxs0lF3mYW3OF9Pr0/oTS zzhrKyFnyc85xM2MRVWxai0I/VJRr0qF8vcqDTbqMZxLK3qYUreyz50FBtFkAJvSVk13uDR9Ssm r15M4EqoZI7zEVN/aDutSFP6r7rWw2KdF30cl57amV32XPa/U+lwYFAWDSP9/BMTHRgGpcx/Gcy fq5alKIj1TikcI6GrRg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-16_01,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 adultscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604160034 ++ Wesley Cheng On Mon, Apr 13, 2026 at 01:18:16PM +0200, Konrad Dybcio wrote: > On 4/13/26 9:06 AM, Qiang Yu wrote: > > On Thu, Apr 09, 2026 at 08:19:41AM -0500, Bjorn Andersson wrote: > >> On Wed, Apr 01, 2026 at 09:47:38PM -0700, Qiang Yu wrote: > >>> On Wed, Apr 01, 2026 at 10:05:12PM +0530, Taniya Das wrote: > >>>> On 4/1/2026 12:05 PM, Qiang Yu wrote: > >>>>> diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-glymur.c > >> [..] > >>>>> +static const char * const tcsr_pcie_4_regulators[] = { > >>>>> + "vdda-refgen-0p9", > >>>>> + "vdda-refgen-1p2", > >>>>> + "vdda-qreftx1-0p9", > >>>>> + "vdda-qrefrpt0-0p9", > >>>>> + "vdda-qrefrpt1-0p9", > >>>>> + "vdda-qrefrpt2-0p9", > >>>>> + "vdda-qrefrx2-0p9", > >>>>> +}; > >>>>> + > >>>> > >>>> TCSR clock refs are just not for PCIe alone, they would have supplies > >>>> for all the ref clocks. These supplies can also be shared across other > >>>> clock refs. I think it is not the correct way to handle the supplies, as > >>>> TCSR does not have the complete supplies map. > >>>> > >>> We have complete supplies map. You can get it on ipcatlog. Here is example > >>> for other instances eg USB and EDP: > >>> - Glymur (eDP): CXO PAD -> TX0 -> RPT0 -> RX0 -> eDP > >>> - Glymur (USB4_2): CXO PAD -> TX0 -> RPT0 -> RPT1 -> RX1 -> USB4_2 > >>> - Glymur (USB3): CXO PAD -> TX0 -> RPT3 -> RPT4 -> RX4 -> USB3_SS3 > >>> > >>> I only add supplies for PCIe in this series because USB and EDP vote these > >>> LDO in their PHY driver. They can remove them in PHY dts node and add same > >>> regulator list here. > >>> > >> > >> The regulators are reference counted. Can't we add the USB and eDP > >> handling here as well now, and then after they are voted here we remove > >> them from the PHY? > >> > > > > For USB, I’m not yet sure which tcsr_*_clkref_en each USB instance in the > > QREF diagram is tied to. I need to confirm that mapping first, I'm > > checking with Wesley Cheng. > > I think on at least some platforms the reference clock for the primary > USB controller is not sw-controllable (so we wouldn't get a handle to > toggle the regulator this way).. please check that > > Konrad