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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e53ccd2564sm13637143eec.18.2026.04.20.00.23.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 00:23:21 -0700 (PDT) Date: Mon, 20 Apr 2026 00:23:19 -0700 From: Qiang Yu To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 1/5] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add support for glymur Gen5 x8 bifurcation mode Message-ID: References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> <20260412-glymur_gen5x8_phy_0413-v3-1-affcebc16b8b@oss.qualcomm.com> <20260415-wooden-prawn-of-lightning-dc1ddc@quoll> <20260417-awesome-tacky-coot-e59a30@quoll> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260417-awesome-tacky-coot-e59a30@quoll> X-Proofpoint-GUID: PbHKeLrMlKzwoqiAR3YbpBUChY3RnRgU X-Proofpoint-ORIG-GUID: PbHKeLrMlKzwoqiAR3YbpBUChY3RnRgU X-Authority-Analysis: v=2.4 cv=SNFykuvH c=1 sm=1 tr=0 ts=69e5d46b cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=AG9yAhbetzltrioosGgA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDA3MSBTYWx0ZWRfX4MEOtQXpu/MF JFsL8sMLDKavMjbin7WG4numDTbdqbSMbHmi1O8YD6noD79geMzWKY6VGmcrZ2kbsOztHIG5OZQ bok/JmULsruWnq4j6Bz4EXeLFrIGDU8mQTZBl3V5KnWHGsuvgLjLPVslvUU/dgb6AnVGl+KUjja IPGW+c7zWvwjsKl2Thkb9yj5lk5AGxDOLoFiiZ0ka8i3U3yfNOC66hcQyIQIB2Lh80nbeux1e1F bT2GNOi/8LaHa4nQutAoUZa5M7ws2/A3E5oouiPL2zrSVRpeb/1mFLzlq77r7MH6wJ3gEEHkdjD tVY3VZ4iR2Xal9zF2w21IZjYzd/xYqNWsR/dFKW6N1MaYn2c0Z9ihLLAiiKerobEAe5cCY87jpe y2V4PCSx5oywYwbDRgal1kgxDQTMR5FC3+J7T5gm3SPJ5L3ILRQ6aplK9DoT/TA6xt0VMEUq3r2 wB6Z58ii7mNVn5buabQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-20_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200071 On Fri, Apr 17, 2026 at 11:18:08AM +0200, Krzysztof Kozlowski wrote: > On Wed, Apr 15, 2026 at 07:58:13PM -0700, Qiang Yu wrote: > > On Wed, Apr 15, 2026 at 09:50:28AM +0200, Krzysztof Kozlowski wrote: > > > On Sun, Apr 12, 2026 at 11:25:56PM -0700, Qiang Yu wrote: > > > > The Glymur SoC has pcie3a and pcie3b PHYs that can operate in two modes: > > > > > > > > 1. Independent 4-lane mode: Each PHY operates as a separate PCIe Gen5 > > > > 4-lane interface, compatible with qcom,glymur-qmp-gen5x4-pcie-phy > > > > 2. Bifurcation mode (8-lane): pcie3a phy acts as leader and pcie3b phy as > > > > follower to form a single 8-lane PCIe Gen5 interface > > > > > > > > In bifurcation mode, the hardware design requires controlling additional > > > > resources beyond the standard pcie3a PHY configuration: > > > > > > > > - pcie3b's aux_clk (phy_b_aux) > > > > - pcie3b's phy_gdsc power domain > > > > - pcie3b's bcr/nocsr reset > > > > > > > > Add qcom,glymur-qmp-gen5x8-pcie-phy compatible string to document this > > > > 8-lane bifurcation configuration. > > > > > > Do you describe PCI3A or PCI3B or something combined PCI3? > > > > I describe a single x8 PHY with resources from both the pcie3a and pcie3b > > PHY blocks for x8 operation. > > > > > > > > > > > > > The phy_b_aux clock is used as the 6th clock instead of pipediv2, > > > > requiring the clock-names enum to be extended to support both > > > > [phy_b_aux, pipediv2] options at index 5. This follows the existing > > > > pattern used for [rchng, refgen] clocks at index 3. > > > > > > > > Signed-off-by: Qiang Yu > > > > --- > > > > .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 53 ++++++++++++++++++---- > > > > 1 file changed, 45 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > > > index 3a35120a77ec0ceb814a1cdcacff32fef32b4f7b..14eba5d705b1956c1bb00cc8c95171ed6488299b 100644 > > > > --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > > > +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml > > > > @@ -18,6 +18,7 @@ properties: > > > > enum: > > > > - qcom,glymur-qmp-gen4x2-pcie-phy > > > > - qcom,glymur-qmp-gen5x4-pcie-phy > > > > + - qcom,glymur-qmp-gen5x8-pcie-phy > > > > > > That's the same device as 5x4, no? One device, one compatible and this > > > suggests you will have three PCI phys in the DT - two 5x4 and one 5x8? > > > > > > > It is not the same as the 5x4 PHY. In DT, we model three PHY nodes: > > phy_3a (1x4), phy_3b (1x4), and a separate phy_1x8 node for x8 mode. > > OK, that's what I wanted to hear. And that's what should not be done, > > You should not have a separate node for the same hardware. First, DTC > will give you a W=1 warning, although warning itself should be moved to > W=2. > > Second, the warning tells important story - same hardware is described > twice. > > You only need phy_3a and phy_3b, so only two in total. We can keep only phy_3a and phy_3b, but still add new compatible qcom,glymur-qmp-gen5x8-pcie-phy in binding, right? For boards that support pcie3a(1x4) + pcie3b(1x4), DTS would be: pcie3a_phy { compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; }; pcie3b_phy { compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; }; For boards that support 1x8, we would override pcie3a_phy with: pcie3a_phy { compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; /* additional resources */ }; pcie3b_phy { compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; }; This still uses only two PHY nodes and DTC will not report warning. - Qiang Yu > > phy_3a could have resources of phy_3b OR could have a phandle to > companion (follower) phy to fetch resources from it. I don't know yet > which choice is better, though. > > Best regards, > Krzysztof >